452 UseAVX = 3;
453 UseSSE = 2;
454 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
455 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
456 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
457 #ifdef _LP64
458 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
459 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
460 #endif
461
462 #ifdef _WINDOWS
463 #ifdef _LP64
464 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
465 __ addptr(rsp, 64);
466 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
467 __ addptr(rsp, 64);
468 #endif // _LP64
469 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
470 __ addptr(rsp, 64);
471 #endif // _WINDOWS
472 VM_Version::clean_cpuFeatures();
473 UseAVX = saved_useavx;
474 UseSSE = saved_usesse;
475 __ jmp(wrapup);
476 }
477
478 __ bind(legacy_save_restore);
479 // AVX check
480 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
481 UseAVX = 1;
482 UseSSE = 2;
483 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
484 __ vmovdqu(Address(rsi, 0), xmm0);
485 __ vmovdqu(Address(rsi, 32), xmm7);
486 #ifdef _LP64
487 __ vmovdqu(Address(rsi, 64), xmm8);
488 __ vmovdqu(Address(rsi, 96), xmm15);
489 #endif
490
491 #ifdef _WINDOWS
492 #ifdef _LP64
493 __ vmovdqu(xmm15, Address(rsp, 0));
494 __ addptr(rsp, 32);
495 __ vmovdqu(xmm8, Address(rsp, 0));
496 __ addptr(rsp, 32);
497 #endif // _LP64
498 __ vmovdqu(xmm7, Address(rsp, 0));
499 __ addptr(rsp, 32);
500 #endif // _WINDOWS
501 VM_Version::clean_cpuFeatures();
502 UseAVX = saved_useavx;
503 UseSSE = saved_usesse;
504
505 __ bind(wrapup);
506 __ popf();
507 __ pop(rsi);
508 __ pop(rbx);
509 __ pop(rbp);
510 __ ret(0);
511
512 # undef __
513
514 return start;
515 };
516 };
517
518 void VM_Version::get_processor_features() {
519
520 _cpu = 4; // 486 by default
602 } else if (UseAVX > 0 && supports_avx()) {
603 UseAVX = 1;
604 } else {
605 UseAVX = 0;
606 }
607 } else if (UseAVX < 0) {
608 UseAVX = 0;
609 }
610
611 if (UseAVX < 3) {
612 _features &= ~CPU_AVX512F;
613 _features &= ~CPU_AVX512DQ;
614 _features &= ~CPU_AVX512CD;
615 _features &= ~CPU_AVX512BW;
616 _features &= ~CPU_AVX512VL;
617 }
618
619 if (UseAVX < 2)
620 _features &= ~CPU_AVX2;
621
622 if (UseAVX < 1)
623 _features &= ~CPU_AVX;
624
625 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
626 _features &= ~CPU_AES;
627
628 if (logical_processors_per_package() == 1) {
629 // HT processor could be installed on a system which doesn't support HT.
630 _features &= ~CPU_HT;
631 }
632
633 char buf[256];
634 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
635 cores_per_cpu(), threads_per_core(),
636 cpu_family(), _model, _stepping,
637 (supports_cmov() ? ", cmov" : ""),
638 (supports_cmpxchg8() ? ", cx8" : ""),
639 (supports_fxsr() ? ", fxsr" : ""),
640 (supports_mmx() ? ", mmx" : ""),
641 (supports_sse() ? ", sse" : ""),
642 (supports_sse2() ? ", sse2" : ""),
643 (supports_sse3() ? ", sse3" : ""),
644 (supports_ssse3()? ", ssse3": ""),
645 (supports_sse4_1() ? ", sse4.1" : ""),
646 (supports_sse4_2() ? ", sse4.2" : ""),
647 (supports_popcnt() ? ", popcnt" : ""),
648 (supports_avx() ? ", avx" : ""),
649 (supports_avx2() ? ", avx2" : ""),
650 (supports_aes() ? ", aes" : ""),
651 (supports_clmul() ? ", clmul" : ""),
652 (supports_erms() ? ", erms" : ""),
901 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
902 // setting during arguments processing. See use_biased_locking().
903 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
904 }
905 #endif
906
907 #ifdef COMPILER2
908 if (UseFPUForSpilling) {
909 if (UseSSE < 2) {
910 // Only supported with SSE2+
911 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
912 }
913 }
914 #endif
915 #if defined(COMPILER2) || INCLUDE_JVMCI
916 if (MaxVectorSize > 0) {
917 if (!is_power_of_2(MaxVectorSize)) {
918 warning("MaxVectorSize must be a power of 2");
919 FLAG_SET_DEFAULT(MaxVectorSize, 64);
920 }
921 if (MaxVectorSize > 64) {
922 FLAG_SET_DEFAULT(MaxVectorSize, 64);
923 }
924 if (MaxVectorSize > 16 && (UseAVX == 0 || !os_supports_avx_vectors())) {
925 // 32 bytes vectors (in YMM) are only supported with AVX+
926 FLAG_SET_DEFAULT(MaxVectorSize, 16);
927 }
928 if (UseSSE < 2) {
929 // Vectors (in XMM) are only supported with SSE2+
930 FLAG_SET_DEFAULT(MaxVectorSize, 0);
931 }
932 #if defined(COMPILER2) && defined(ASSERT)
933 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
934 tty->print_cr("State of YMM registers after signal handle:");
935 int nreg = 2 LP64_ONLY(+2);
936 const char* ymm_name[4] = {"0", "7", "8", "15"};
937 for (int i = 0; i < nreg; i++) {
938 tty->print("YMM%s:", ymm_name[i]);
939 for (int j = 7; j >=0; j--) {
940 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
941 }
942 tty->cr();
943 }
944 }
945 #endif // COMPILER2 && ASSERT
946 }
947 #endif // COMPILER2 || INCLUDE_JVMCI
948
949 #ifdef COMPILER2
950 #ifdef _LP64
|
452 UseAVX = 3;
453 UseSSE = 2;
454 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
455 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
456 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
457 #ifdef _LP64
458 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
459 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
460 #endif
461
462 #ifdef _WINDOWS
463 #ifdef _LP64
464 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
465 __ addptr(rsp, 64);
466 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
467 __ addptr(rsp, 64);
468 #endif // _LP64
469 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
470 __ addptr(rsp, 64);
471 #endif // _WINDOWS
472 __ vzeroupper();
473 VM_Version::clean_cpuFeatures();
474 UseAVX = saved_useavx;
475 UseSSE = saved_usesse;
476 __ jmp(wrapup);
477 }
478
479 __ bind(legacy_save_restore);
480 // AVX check
481 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
482 UseAVX = 1;
483 UseSSE = 2;
484 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
485 __ vmovdqu(Address(rsi, 0), xmm0);
486 __ vmovdqu(Address(rsi, 32), xmm7);
487 #ifdef _LP64
488 __ vmovdqu(Address(rsi, 64), xmm8);
489 __ vmovdqu(Address(rsi, 96), xmm15);
490 #endif
491
492 #ifdef _WINDOWS
493 #ifdef _LP64
494 __ vmovdqu(xmm15, Address(rsp, 0));
495 __ addptr(rsp, 32);
496 __ vmovdqu(xmm8, Address(rsp, 0));
497 __ addptr(rsp, 32);
498 #endif // _LP64
499 __ vmovdqu(xmm7, Address(rsp, 0));
500 __ addptr(rsp, 32);
501 #endif // _WINDOWS
502 __ vzeroupper();
503 VM_Version::clean_cpuFeatures();
504 UseAVX = saved_useavx;
505 UseSSE = saved_usesse;
506
507 __ bind(wrapup);
508 __ popf();
509 __ pop(rsi);
510 __ pop(rbx);
511 __ pop(rbp);
512 __ ret(0);
513
514 # undef __
515
516 return start;
517 };
518 };
519
520 void VM_Version::get_processor_features() {
521
522 _cpu = 4; // 486 by default
604 } else if (UseAVX > 0 && supports_avx()) {
605 UseAVX = 1;
606 } else {
607 UseAVX = 0;
608 }
609 } else if (UseAVX < 0) {
610 UseAVX = 0;
611 }
612
613 if (UseAVX < 3) {
614 _features &= ~CPU_AVX512F;
615 _features &= ~CPU_AVX512DQ;
616 _features &= ~CPU_AVX512CD;
617 _features &= ~CPU_AVX512BW;
618 _features &= ~CPU_AVX512VL;
619 }
620
621 if (UseAVX < 2)
622 _features &= ~CPU_AVX2;
623
624 if (UseAVX < 1) {
625 _features &= ~CPU_AVX;
626 _features &= ~CPU_VZEROUPPER;
627 }
628
629 if (!UseAES && !FLAG_IS_DEFAULT(UseAES))
630 _features &= ~CPU_AES;
631
632 if (logical_processors_per_package() == 1) {
633 // HT processor could be installed on a system which doesn't support HT.
634 _features &= ~CPU_HT;
635 }
636
637 if( is_intel() ) { // Intel cpus specific settings
638 if ((cpu_family() == 0x06) &&
639 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
640 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
641 _features &= ~CPU_VZEROUPPER;
642 }
643 }
644
645 char buf[256];
646 jio_snprintf(buf, sizeof(buf), "(%u cores per cpu, %u threads per core) family %d model %d stepping %d%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
647 cores_per_cpu(), threads_per_core(),
648 cpu_family(), _model, _stepping,
649 (supports_cmov() ? ", cmov" : ""),
650 (supports_cmpxchg8() ? ", cx8" : ""),
651 (supports_fxsr() ? ", fxsr" : ""),
652 (supports_mmx() ? ", mmx" : ""),
653 (supports_sse() ? ", sse" : ""),
654 (supports_sse2() ? ", sse2" : ""),
655 (supports_sse3() ? ", sse3" : ""),
656 (supports_ssse3()? ", ssse3": ""),
657 (supports_sse4_1() ? ", sse4.1" : ""),
658 (supports_sse4_2() ? ", sse4.2" : ""),
659 (supports_popcnt() ? ", popcnt" : ""),
660 (supports_avx() ? ", avx" : ""),
661 (supports_avx2() ? ", avx2" : ""),
662 (supports_aes() ? ", aes" : ""),
663 (supports_clmul() ? ", clmul" : ""),
664 (supports_erms() ? ", erms" : ""),
913 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
914 // setting during arguments processing. See use_biased_locking().
915 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
916 }
917 #endif
918
919 #ifdef COMPILER2
920 if (UseFPUForSpilling) {
921 if (UseSSE < 2) {
922 // Only supported with SSE2+
923 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
924 }
925 }
926 #endif
927 #if defined(COMPILER2) || INCLUDE_JVMCI
928 if (MaxVectorSize > 0) {
929 if (!is_power_of_2(MaxVectorSize)) {
930 warning("MaxVectorSize must be a power of 2");
931 FLAG_SET_DEFAULT(MaxVectorSize, 64);
932 }
933 if (UseSSE < 2) {
934 // Vectors (in XMM) are only supported with SSE2+
935 if (MaxVectorSize > 0) {
936 if (!FLAG_IS_DEFAULT(MaxVectorSize))
937 warning("MaxVectorSize must be 0");
938 FLAG_SET_DEFAULT(MaxVectorSize, 0);
939 }
940 }
941 else if (UseAVX == 0 || !os_supports_avx_vectors()) {
942 // 32 bytes vectors (in YMM) are only supported with AVX+
943 if (MaxVectorSize > 16) {
944 if (!FLAG_IS_DEFAULT(MaxVectorSize))
945 warning("MaxVectorSize must be <= 16");
946 FLAG_SET_DEFAULT(MaxVectorSize, 16);
947 }
948 }
949 else if (UseAVX == 1 || UseAVX == 2) {
950 // 64 bytes vectors (in ZMM) are only supported with AVX 3
951 if (MaxVectorSize > 32) {
952 if (!FLAG_IS_DEFAULT(MaxVectorSize))
953 warning("MaxVectorSize must be <= 32");
954 FLAG_SET_DEFAULT(MaxVectorSize, 32);
955 }
956 }
957 else if (UseAVX > 2 ) {
958 if (MaxVectorSize > 64) {
959 if (!FLAG_IS_DEFAULT(MaxVectorSize))
960 warning("MaxVectorSize must be <= 64");
961 FLAG_SET_DEFAULT(MaxVectorSize, 64);
962 }
963 }
964 #if defined(COMPILER2) && defined(ASSERT)
965 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
966 tty->print_cr("State of YMM registers after signal handle:");
967 int nreg = 2 LP64_ONLY(+2);
968 const char* ymm_name[4] = {"0", "7", "8", "15"};
969 for (int i = 0; i < nreg; i++) {
970 tty->print("YMM%s:", ymm_name[i]);
971 for (int j = 7; j >=0; j--) {
972 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
973 }
974 tty->cr();
975 }
976 }
977 #endif // COMPILER2 && ASSERT
978 }
979 #endif // COMPILER2 || INCLUDE_JVMCI
980
981 #ifdef COMPILER2
982 #ifdef _LP64
|