274 CPU_AVX2 = (1 << 18),
275 CPU_AES = (1 << 19),
276 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
277 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
278 CPU_BMI1 = (1 << 22),
279 CPU_BMI2 = (1 << 23),
280 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
281 CPU_ADX = (1 << 25),
282 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
283 CPU_AVX512DQ = (1 << 27),
284 CPU_AVX512PF = (1 << 28),
285 CPU_AVX512ER = (1 << 29),
286 CPU_AVX512CD = (1 << 30)
287 // Keeping sign bit 31 unassigned.
288 };
289
290 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
291 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
292 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
293 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
294
295 enum Extended_Family {
296 // AMD
297 CPU_FAMILY_AMD_11H = 0x11,
298 // Intel
299 CPU_FAMILY_INTEL_CORE = 6,
300 CPU_MODEL_NEHALEM = 0x1e,
301 CPU_MODEL_NEHALEM_EP = 0x1a,
302 CPU_MODEL_NEHALEM_EX = 0x2e,
303 CPU_MODEL_WESTMERE = 0x25,
304 CPU_MODEL_WESTMERE_EP = 0x2c,
305 CPU_MODEL_WESTMERE_EX = 0x2f,
306 CPU_MODEL_SANDYBRIDGE = 0x2a,
307 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
308 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
309 CPU_MODEL_HASWELL_E3 = 0x3c,
310 CPU_MODEL_HASWELL_E7 = 0x3f,
311 CPU_MODEL_BROADWELL = 0x3d,
312 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
313 };
451 result |= CPU_MMX;
452 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
453 result |= CPU_SSE;
454 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
455 result |= CPU_SSE2;
456 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
457 result |= CPU_SSE3;
458 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
459 result |= CPU_SSSE3;
460 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
461 result |= CPU_SSE4_1;
462 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
463 result |= CPU_SSE4_2;
464 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
465 result |= CPU_POPCNT;
466 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
467 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
468 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
469 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
470 result |= CPU_AVX;
471 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
472 result |= CPU_AVX2;
473 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
474 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
475 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
476 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
477 result |= CPU_AVX512F;
478 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
479 result |= CPU_AVX512CD;
480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
481 result |= CPU_AVX512DQ;
482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
483 result |= CPU_AVX512PF;
484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
485 result |= CPU_AVX512ER;
486 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
487 result |= CPU_AVX512BW;
488 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
489 result |= CPU_AVX512VL;
490 }
588 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
589 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
590 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
591 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
592 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
593 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
594 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
595 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
596 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
597
598 // The value used to check ymm register after signal handle
599 static int ymm_test_value() { return 0xCAFEBABE; }
600
601 static void get_cpu_info_wrapper();
602 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
603 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
604 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
605 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
606
607 static void clean_cpuFeatures() { _features = 0; }
608 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX); }
609 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 ); }
610
611
612 // Initialization
613 static void initialize();
614
615 // Override Abstract_VM_Version implementation
616 static bool use_biased_locking();
617
618 // Asserts
619 static void assert_is_initialized() {
620 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
621 }
622
623 //
624 // Processor family:
625 // 3 - 386
626 // 4 - 486
627 // 5 - Pentium
628 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
629 // Pentium M, Core Solo, Core Duo, Core2 Duo
714 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
715 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
716 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
717 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
718 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
719 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
720 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
721 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
722 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
723 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
724 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
725 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
726 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
727 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
728 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
729 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
730 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
731 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
732 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
733 static bool supports_fma() { return (_features & CPU_FMA) != 0; }
734 // Intel features
735 static bool is_intel_family_core() { return is_intel() &&
736 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
737
738 static bool is_intel_tsc_synched_at_init() {
739 if (is_intel_family_core()) {
740 uint32_t ext_model = extended_cpu_model();
741 if (ext_model == CPU_MODEL_NEHALEM_EP ||
742 ext_model == CPU_MODEL_WESTMERE_EP ||
743 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
744 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
745 // <= 2-socket invariant tsc support. EX versions are usually used
746 // in > 2-socket systems and likely don't synchronize tscs at
747 // initialization.
748 // Code that uses tsc values must be prepared for them to arbitrarily
749 // jump forward or backward.
750 return true;
751 }
752 }
753 return false;
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274 CPU_AVX2 = (1 << 18),
275 CPU_AES = (1 << 19),
276 CPU_ERMS = (1 << 20), // enhanced 'rep movsb/stosb' instructions
277 CPU_CLMUL = (1 << 21), // carryless multiply for CRC
278 CPU_BMI1 = (1 << 22),
279 CPU_BMI2 = (1 << 23),
280 CPU_RTM = (1 << 24), // Restricted Transactional Memory instructions
281 CPU_ADX = (1 << 25),
282 CPU_AVX512F = (1 << 26), // AVX 512bit foundation instructions
283 CPU_AVX512DQ = (1 << 27),
284 CPU_AVX512PF = (1 << 28),
285 CPU_AVX512ER = (1 << 29),
286 CPU_AVX512CD = (1 << 30)
287 // Keeping sign bit 31 unassigned.
288 };
289
290 #define CPU_AVX512BW ((uint64_t)UCONST64(0x100000000)) // enums are limited to 31 bit
291 #define CPU_AVX512VL ((uint64_t)UCONST64(0x200000000)) // EVEX instructions with smaller vector length
292 #define CPU_SHA ((uint64_t)UCONST64(0x400000000)) // SHA instructions
293 #define CPU_FMA ((uint64_t)UCONST64(0x800000000)) // FMA instructions
294 #define CPU_VZEROUPPER ((uint64_t)UCONST64(0x1000000000)) // Vzeroupper instruction
295
296 enum Extended_Family {
297 // AMD
298 CPU_FAMILY_AMD_11H = 0x11,
299 // Intel
300 CPU_FAMILY_INTEL_CORE = 6,
301 CPU_MODEL_NEHALEM = 0x1e,
302 CPU_MODEL_NEHALEM_EP = 0x1a,
303 CPU_MODEL_NEHALEM_EX = 0x2e,
304 CPU_MODEL_WESTMERE = 0x25,
305 CPU_MODEL_WESTMERE_EP = 0x2c,
306 CPU_MODEL_WESTMERE_EX = 0x2f,
307 CPU_MODEL_SANDYBRIDGE = 0x2a,
308 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
309 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
310 CPU_MODEL_HASWELL_E3 = 0x3c,
311 CPU_MODEL_HASWELL_E7 = 0x3f,
312 CPU_MODEL_BROADWELL = 0x3d,
313 CPU_MODEL_SKYLAKE = CPU_MODEL_HASWELL_E3
314 };
452 result |= CPU_MMX;
453 if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
454 result |= CPU_SSE;
455 if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
456 result |= CPU_SSE2;
457 if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
458 result |= CPU_SSE3;
459 if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
460 result |= CPU_SSSE3;
461 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
462 result |= CPU_SSE4_1;
463 if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
464 result |= CPU_SSE4_2;
465 if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
466 result |= CPU_POPCNT;
467 if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
468 _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
469 _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
470 _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
471 result |= CPU_AVX;
472 result |= CPU_VZEROUPPER;
473 if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
474 result |= CPU_AVX2;
475 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
476 _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
477 _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
478 _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
479 result |= CPU_AVX512F;
480 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
481 result |= CPU_AVX512CD;
482 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
483 result |= CPU_AVX512DQ;
484 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
485 result |= CPU_AVX512PF;
486 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
487 result |= CPU_AVX512ER;
488 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
489 result |= CPU_AVX512BW;
490 if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
491 result |= CPU_AVX512VL;
492 }
590 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
591 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
592 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
593 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
594 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
595 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
596 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
597 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
598 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
599
600 // The value used to check ymm register after signal handle
601 static int ymm_test_value() { return 0xCAFEBABE; }
602
603 static void get_cpu_info_wrapper();
604 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
605 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
606 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
607 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
608
609 static void clean_cpuFeatures() { _features = 0; }
610 static void set_avx_cpuFeatures() {
611 _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER );
612 if( is_intel() ) { // Intel cpus specific settings
613 if ((cpu_family() == 0x06) &&
614 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
615 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
616 _features &= ~CPU_VZEROUPPER;
617 }
618 }
619 }
620 static void set_evex_cpuFeatures() {
621 _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER );
622 if( is_intel() ) { // Intel cpus specific settings
623 if ((cpu_family() == 0x06) &&
624 ((extended_cpu_model() == 0x57) || // Xeon Phi 3200/5200/7200
625 (extended_cpu_model() == 0x85))) { // Future Xeon Phi
626 _features &= ~CPU_VZEROUPPER;
627 }
628 }
629 }
630
631
632 // Initialization
633 static void initialize();
634
635 // Override Abstract_VM_Version implementation
636 static bool use_biased_locking();
637
638 // Asserts
639 static void assert_is_initialized() {
640 assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
641 }
642
643 //
644 // Processor family:
645 // 3 - 386
646 // 4 - 486
647 // 5 - Pentium
648 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
649 // Pentium M, Core Solo, Core Duo, Core2 Duo
734 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
735 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
736 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
737 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
738 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
739 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
740 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
741 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
742 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
743 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
744 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
745 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
746 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
747 static bool supports_avx512vlbw() { return (supports_avx512bw() && supports_avx512vl()); }
748 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
749 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
750 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
751 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
752 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
753 static bool supports_fma() { return (_features & CPU_FMA) != 0; }
754 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
755
756 // Intel features
757 static bool is_intel_family_core() { return is_intel() &&
758 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
759
760 static bool is_intel_tsc_synched_at_init() {
761 if (is_intel_family_core()) {
762 uint32_t ext_model = extended_cpu_model();
763 if (ext_model == CPU_MODEL_NEHALEM_EP ||
764 ext_model == CPU_MODEL_WESTMERE_EP ||
765 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
766 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
767 // <= 2-socket invariant tsc support. EX versions are usually used
768 // in > 2-socket systems and likely don't synchronize tscs at
769 // initialization.
770 // Code that uses tsc values must be prepared for them to arbitrarily
771 // jump forward or backward.
772 return true;
773 }
774 }
775 return false;
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