11800 %}
11801 ins_pipe( pipe_slow );
11802 %}
11803
11804 // encode char[] to byte[] in ISO_8859_1
11805 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11806 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11807 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11808 match(Set result (EncodeISOArray src (Binary dst len)));
11809 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11810
11811 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11812 ins_encode %{
11813 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11814 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11815 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11816 %}
11817 ins_pipe( pipe_slow );
11818 %}
11819
11820
11821 //----------Control Flow Instructions------------------------------------------
11822 // Signed compare Instructions
11823 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11824 match(Set cr (CmpI op1 op2));
11825 effect( DEF cr, USE op1, USE op2 );
11826 format %{ "CMP $op1,$op2" %}
11827 opcode(0x3B); /* Opcode 3B /r */
11828 ins_encode( OpcP, RegReg( op1, op2) );
11829 ins_pipe( ialu_cr_reg_reg );
11830 %}
11831
11832 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11833 match(Set cr (CmpI op1 op2));
11834 effect( DEF cr, USE op1 );
11835 format %{ "CMP $op1,$op2" %}
11836 opcode(0x81,0x07); /* Opcode 81 /7 */
11837 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11838 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11839 ins_pipe( ialu_cr_reg_imm );
|
11800 %}
11801 ins_pipe( pipe_slow );
11802 %}
11803
11804 // encode char[] to byte[] in ISO_8859_1
11805 instruct encode_iso_array(eSIRegP src, eDIRegP dst, eDXRegI len,
11806 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
11807 eCXRegI tmp5, eAXRegI result, eFlagsReg cr) %{
11808 match(Set result (EncodeISOArray src (Binary dst len)));
11809 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11810
11811 format %{ "Encode array $src,$dst,$len -> $result // KILL ECX, EDX, $tmp1, $tmp2, $tmp3, $tmp4, ESI, EDI " %}
11812 ins_encode %{
11813 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11814 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11815 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
11816 %}
11817 ins_pipe( pipe_slow );
11818 %}
11819
11820 // fma - double - a * b + c
11821 instruct fmaD_reg(regD a, regD b, regD c) %{
11822 predicate(UseFMA);
11823 match(Set c (FmaD c (Binary a b)));
11824 format %{ "fmasd $a,$b,$c -> $c" %}
11825 ins_cost(150);
11826 ins_encode %{
11827 __ vfmadd231sd($c$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister);
11828 %}
11829 ins_pipe( pipe_slow );
11830 %}
11831
11832 // fma - float - a * b + c
11833 instruct fmaF_reg(regF a, regF b, regF c) %{
11834 predicate(UseFMA);
11835 match(Set c (FmaF c (Binary a b)));
11836 format %{ "fmass $a,$b,$c -> $c" %}
11837 ins_cost(150);
11838 ins_encode %{
11839 __ vfmadd231ss($c$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister);
11840 %}
11841 ins_pipe( pipe_slow );
11842 %}
11843
11844
11845 //----------Control Flow Instructions------------------------------------------
11846 // Signed compare Instructions
11847 instruct compI_eReg(eFlagsReg cr, rRegI op1, rRegI op2) %{
11848 match(Set cr (CmpI op1 op2));
11849 effect( DEF cr, USE op1, USE op2 );
11850 format %{ "CMP $op1,$op2" %}
11851 opcode(0x3B); /* Opcode 3B /r */
11852 ins_encode( OpcP, RegReg( op1, op2) );
11853 ins_pipe( ialu_cr_reg_reg );
11854 %}
11855
11856 instruct compI_eReg_imm(eFlagsReg cr, rRegI op1, immI op2) %{
11857 match(Set cr (CmpI op1 op2));
11858 effect( DEF cr, USE op1 );
11859 format %{ "CMP $op1,$op2" %}
11860 opcode(0x81,0x07); /* Opcode 81 /7 */
11861 // ins_encode( RegImm( op1, op2) ); /* Was CmpImm */
11862 ins_encode( OpcSErm( op1, op2 ), Con8or32( op2 ) );
11863 ins_pipe( ialu_cr_reg_imm );
|