10934 %}
10935 ins_pipe( pipe_slow );
10936 %}
10937
10938 // encode char[] to byte[] in ISO_8859_1
10939 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10940 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10941 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10942 match(Set result (EncodeISOArray src (Binary dst len)));
10943 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10944
10945 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10946 ins_encode %{
10947 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10948 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10949 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 //----------Overflow Math Instructions-----------------------------------------
10955
10956 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10957 %{
10958 match(Set cr (OverflowAddI op1 op2));
10959 effect(DEF cr, USE_KILL op1, USE op2);
10960
10961 format %{ "addl $op1, $op2\t# overflow check int" %}
10962
10963 ins_encode %{
10964 __ addl($op1$$Register, $op2$$Register);
10965 %}
10966 ins_pipe(ialu_reg_reg);
10967 %}
10968
10969 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10970 %{
10971 match(Set cr (OverflowAddI op1 op2));
10972 effect(DEF cr, USE_KILL op1, USE op2);
10973
|
10934 %}
10935 ins_pipe( pipe_slow );
10936 %}
10937
10938 // encode char[] to byte[] in ISO_8859_1
10939 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10940 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10941 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10942 match(Set result (EncodeISOArray src (Binary dst len)));
10943 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10944
10945 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10946 ins_encode %{
10947 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10948 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10949 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10950 %}
10951 ins_pipe( pipe_slow );
10952 %}
10953
10954 // fma - double - a * b + c
10955 instruct fmaD_reg(regD a, regD b, regD c) %{
10956 predicate(UseFMA);
10957 match(Set c (FmaD c (Binary a b)));
10958 format %{ "fmasd $a,$b,$c -> $c" %}
10959 ins_cost(150);
10960 ins_encode %{
10961 __ vfmadd231sd($c$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister);
10962 %}
10963 ins_pipe( pipe_slow );
10964 %}
10965
10966 // fma - float - a * b + c
10967 instruct fmaF_reg(regF a, regF b, regF c) %{
10968 predicate(UseFMA);
10969 match(Set c (FmaF c (Binary a b)));
10970 format %{ "fmass $a,$b,$c -> $c" %}
10971 ins_cost(150);
10972 ins_encode %{
10973 __ vfmadd231ss($c$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister);
10974 %}
10975 ins_pipe( pipe_slow );
10976 %}
10977
10978 //----------Overflow Math Instructions-----------------------------------------
10979
10980 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10981 %{
10982 match(Set cr (OverflowAddI op1 op2));
10983 effect(DEF cr, USE_KILL op1, USE op2);
10984
10985 format %{ "addl $op1, $op2\t# overflow check int" %}
10986
10987 ins_encode %{
10988 __ addl($op1$$Register, $op2$$Register);
10989 %}
10990 ins_pipe(ialu_reg_reg);
10991 %}
10992
10993 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10994 %{
10995 match(Set cr (OverflowAddI op1 op2));
10996 effect(DEF cr, USE_KILL op1, USE op2);
10997
|