2351 {
2352 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2353 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2354 }
2355 __ andpd(dest->as_xmm_double_reg(),
2356 ExternalAddress((address)double_signmask_pool));
2357 }
2358 break;
2359
2360 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2361 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2362 default : ShouldNotReachHere();
2363 }
2364
2365 } else if (value->is_double_fpu()) {
2366 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2367 switch(code) {
2368 case lir_log10 : __ flog10() ; break;
2369 case lir_abs : __ fabs() ; break;
2370 case lir_sqrt : __ fsqrt(); break;
2371 case lir_sin :
2372 // Should consider not saving rbx, if not necessary
2373 __ trigfunc('s', op->as_Op2()->fpu_stack_size());
2374 break;
2375 case lir_cos :
2376 // Should consider not saving rbx, if not necessary
2377 assert(op->as_Op2()->fpu_stack_size() <= 6, "sin and cos need two free stack slots");
2378 __ trigfunc('c', op->as_Op2()->fpu_stack_size());
2379 break;
2380 case lir_tan :
2381 // Should consider not saving rbx, if not necessary
2382 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2383 break;
2384 default : ShouldNotReachHere();
2385 }
2386 } else {
2387 Unimplemented();
2388 }
2389 }
2390
2391 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2392 // assert(left->destroys_register(), "check");
2393 if (left->is_single_cpu()) {
2394 Register reg = left->as_register();
2395 if (right->is_constant()) {
2396 int val = right->as_constant_ptr()->as_jint();
2397 switch (code) {
2398 case lir_logic_and: __ andl (reg, val); break;
2399 case lir_logic_or: __ orl (reg, val); break;
|
2351 {
2352 if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2353 __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2354 }
2355 __ andpd(dest->as_xmm_double_reg(),
2356 ExternalAddress((address)double_signmask_pool));
2357 }
2358 break;
2359
2360 case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2361 // all other intrinsics are not available in the SSE instruction set, so FPU is used
2362 default : ShouldNotReachHere();
2363 }
2364
2365 } else if (value->is_double_fpu()) {
2366 assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2367 switch(code) {
2368 case lir_log10 : __ flog10() ; break;
2369 case lir_abs : __ fabs() ; break;
2370 case lir_sqrt : __ fsqrt(); break;
2371 case lir_tan :
2372 // Should consider not saving rbx, if not necessary
2373 __ trigfunc('t', op->as_Op2()->fpu_stack_size());
2374 break;
2375 default : ShouldNotReachHere();
2376 }
2377 } else {
2378 Unimplemented();
2379 }
2380 }
2381
2382 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2383 // assert(left->destroys_register(), "check");
2384 if (left->is_single_cpu()) {
2385 Register reg = left->as_register();
2386 if (right->is_constant()) {
2387 int val = right->as_constant_ptr()->as_jint();
2388 switch (code) {
2389 case lir_logic_and: __ andl (reg, val); break;
2390 case lir_logic_or: __ orl (reg, val); break;
|