9811 format %{ "SUB ESP,8\t # DMOD\n"
9812 "\tMOVSD [ESP+0],$src1\n"
9813 "\tFLD_D [ESP+0]\n"
9814 "\tMOVSD [ESP+0],$src0\n"
9815 "\tFLD_D [ESP+0]\n"
9816 "loop:\tFPREM\n"
9817 "\tFWAIT\n"
9818 "\tFNSTSW AX\n"
9819 "\tSAHF\n"
9820 "\tJP loop\n"
9821 "\tFSTP_D [ESP+0]\n"
9822 "\tMOVSD $dst,[ESP+0]\n"
9823 "\tADD ESP,8\n"
9824 "\tFSTP ST0\t # Restore FPU Stack"
9825 %}
9826 ins_cost(250);
9827 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct tanDPR_reg(regDPR1 dst, regDPR1 src) %{
9832 predicate (UseSSE<=1);
9833 match(Set dst(TanD src));
9834 format %{ "DTAN $dst" %}
9835 ins_encode( Opcode(0xD9), Opcode(0xF2), // fptan
9836 Opcode(0xDD), Opcode(0xD8)); // fstp st
9837 ins_pipe( pipe_slow );
9838 %}
9839
9840 instruct tanD_reg(regD dst, eFlagsReg cr) %{
9841 predicate (UseSSE>=2);
9842 match(Set dst(TanD dst));
9843 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9844 format %{ "DTAN $dst" %}
9845 ins_encode( Push_SrcD(dst),
9846 Opcode(0xD9), Opcode(0xF2), // fptan
9847 Opcode(0xDD), Opcode(0xD8), // fstp st
9848 Push_ResultD(dst) );
9849 ins_pipe( pipe_slow );
9850 %}
9851
9852 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9853 predicate (UseSSE<=1);
9854 match(Set dst(AtanD dst src));
9855 format %{ "DATA $dst,$src" %}
9856 opcode(0xD9, 0xF3);
9857 ins_encode( Push_Reg_DPR(src),
9858 OpcP, OpcS, RegOpc(dst) );
9859 ins_pipe( pipe_slow );
9860 %}
9861
9862 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9863 predicate (UseSSE>=2);
9864 match(Set dst(AtanD dst src));
9865 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9866 format %{ "DATA $dst,$src" %}
9867 opcode(0xD9, 0xF3);
9868 ins_encode( Push_SrcD(src),
9869 OpcP, OpcS, Push_ResultD(dst) );
9870 ins_pipe( pipe_slow );
9871 %}
9872
9873 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9874 predicate (UseSSE<=1);
9875 match(Set dst (SqrtD src));
9876 format %{ "DSQRT $dst,$src" %}
9877 opcode(0xFA, 0xD9);
9878 ins_encode( Push_Reg_DPR(src),
9879 OpcS, OpcP, Pop_Reg_DPR(dst) );
9880 ins_pipe( pipe_slow );
9881 %}
9882
9883 instruct log10DPR_reg(regDPR1 dst, regDPR1 src) %{
9884 predicate (UseSSE<=1);
9885 // The source Double operand on FPU stack
9886 match(Set dst (Log10D src));
9887 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9888 // fxch ; swap ST(0) with ST(1)
9889 // fyl2x ; compute log_10(2) * log_2(x)
9890 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9891 "FXCH \n\t"
9892 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9893 %}
9894 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9895 Opcode(0xD9), Opcode(0xC9), // fxch
9896 Opcode(0xD9), Opcode(0xF1)); // fyl2x
9897
9898 ins_pipe( pipe_slow );
9899 %}
9900
9901 instruct log10D_reg(regD dst, regD src, eFlagsReg cr) %{
9902 predicate (UseSSE>=2);
9903 effect(KILL cr);
9904 match(Set dst (Log10D src));
9905 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9906 // fyl2x ; compute log_10(2) * log_2(x)
9907 format %{ "FLDLG2 \t\t\t#Log10\n\t"
9908 "FYL2X \t\t\t# Q=Log10*Log_2(x)"
9909 %}
9910 ins_encode( Opcode(0xD9), Opcode(0xEC), // fldlg2
9911 Push_SrcD(src),
9912 Opcode(0xD9), Opcode(0xF1), // fyl2x
9913 Push_ResultD(dst));
9914
9915 ins_pipe( pipe_slow );
9916 %}
9917
9918 //-------------Float Instructions-------------------------------
9919 // Float Math
9920
9921 // Code for float compare:
9922 // fcompp();
9923 // fwait(); fnstsw_ax();
9924 // sahf();
9925 // movl(dst, unordered_result);
9926 // jcc(Assembler::parity, exit);
9927 // movl(dst, less_result);
9928 // jcc(Assembler::below, exit);
9929 // movl(dst, equal_result);
9930 // jcc(Assembler::equal, exit);
9931 // movl(dst, greater_result);
9932 // exit:
9933
9934 // P6 version of float compare, sets condition codes in EFLAGS
|
9811 format %{ "SUB ESP,8\t # DMOD\n"
9812 "\tMOVSD [ESP+0],$src1\n"
9813 "\tFLD_D [ESP+0]\n"
9814 "\tMOVSD [ESP+0],$src0\n"
9815 "\tFLD_D [ESP+0]\n"
9816 "loop:\tFPREM\n"
9817 "\tFWAIT\n"
9818 "\tFNSTSW AX\n"
9819 "\tSAHF\n"
9820 "\tJP loop\n"
9821 "\tFSTP_D [ESP+0]\n"
9822 "\tMOVSD $dst,[ESP+0]\n"
9823 "\tADD ESP,8\n"
9824 "\tFSTP ST0\t # Restore FPU Stack"
9825 %}
9826 ins_cost(250);
9827 ins_encode( Push_ModD_encoding(src0, src1), emitModDPR(), Push_ResultD(dst), PopFPU);
9828 ins_pipe( pipe_slow );
9829 %}
9830
9831 instruct atanDPR_reg(regDPR dst, regDPR src) %{
9832 predicate (UseSSE<=1);
9833 match(Set dst(AtanD dst src));
9834 format %{ "DATA $dst,$src" %}
9835 opcode(0xD9, 0xF3);
9836 ins_encode( Push_Reg_DPR(src),
9837 OpcP, OpcS, RegOpc(dst) );
9838 ins_pipe( pipe_slow );
9839 %}
9840
9841 instruct atanD_reg(regD dst, regD src, eFlagsReg cr) %{
9842 predicate (UseSSE>=2);
9843 match(Set dst(AtanD dst src));
9844 effect(KILL cr); // Push_{Src|Result}D() uses "{SUB|ADD} ESP,8"
9845 format %{ "DATA $dst,$src" %}
9846 opcode(0xD9, 0xF3);
9847 ins_encode( Push_SrcD(src),
9848 OpcP, OpcS, Push_ResultD(dst) );
9849 ins_pipe( pipe_slow );
9850 %}
9851
9852 instruct sqrtDPR_reg(regDPR dst, regDPR src) %{
9853 predicate (UseSSE<=1);
9854 match(Set dst (SqrtD src));
9855 format %{ "DSQRT $dst,$src" %}
9856 opcode(0xFA, 0xD9);
9857 ins_encode( Push_Reg_DPR(src),
9858 OpcS, OpcP, Pop_Reg_DPR(dst) );
9859 ins_pipe( pipe_slow );
9860 %}
9861
9862 //-------------Float Instructions-------------------------------
9863 // Float Math
9864
9865 // Code for float compare:
9866 // fcompp();
9867 // fwait(); fnstsw_ax();
9868 // sahf();
9869 // movl(dst, unordered_result);
9870 // jcc(Assembler::parity, exit);
9871 // movl(dst, less_result);
9872 // jcc(Assembler::below, exit);
9873 // movl(dst, equal_result);
9874 // jcc(Assembler::equal, exit);
9875 // movl(dst, greater_result);
9876 // exit:
9877
9878 // P6 version of float compare, sets condition codes in EFLAGS
|