543 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
544 // location (stack or register).
545 class MachSpillCopyNode : public MachIdealNode {
546 public:
547 enum SpillType {
548 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
549 PhiInput, // Inserted when coalescing of a phi node and its input fails
550 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
551 LoopPhiInput, // Pre-split compares of loop-phis
552 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
553 // if in high pressure region or the lrg is bound
554 RegToReg, // A register to register move
555 RegToMem, // A register to memory move
556 MemToReg, // A memory to register move
557 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
558 // the phi and its input resides at different locations (i.e. reg or mem)
559 BasePointerToMem, // Spill base pointer to memory at safepoint
560 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
561 // stretched beyond a new definition point, therefore we split out new copies instead
562 CallUse, // Spill use at a call
563 Bound // An lrg marked as spill that is bound and needs to be spilled at a use
564 };
565 private:
566 const RegMask *_in; // RegMask for input
567 const RegMask *_out; // RegMask for output
568 const Type *_type;
569 const SpillType _spill_type;
570 public:
571 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
572 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) {
573 init_class_id(Class_MachSpillCopy);
574 init_flags(Flag_is_Copy);
575 add_req(NULL);
576 add_req(n);
577 }
578 virtual uint size_of() const { return sizeof(*this); }
579 void set_out_RegMask(const RegMask &out) { _out = &out; }
580 void set_in_RegMask(const RegMask &in) { _in = ∈ }
581 virtual const RegMask &out_RegMask() const { return *_out; }
582 virtual const RegMask &in_RegMask(uint) const { return *_in; }
583 virtual const class Type *bottom_type() const { return _type; }
584 virtual uint ideal_reg() const { return _type->ideal_reg(); }
585 virtual uint oper_input_base() const { return 1; }
586 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
587
588 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
589 virtual uint size(PhaseRegAlloc *ra_) const;
590
591
592 #ifndef PRODUCT
593 static const char *spill_type(SpillType st) {
594 switch (st) {
595 case TwoAddress:
596 return "TwoAddressSpillCopy";
597 case PhiInput:
598 return "PhiInputSpillCopy";
599 case DebugUse:
600 return "DebugUseSpillCopy";
601 case LoopPhiInput:
602 return "LoopPhiInputSpillCopy";
603 case Definition:
604 return "DefinitionSpillCopy";
605 case RegToReg:
606 return "RegToRegSpillCopy";
607 case RegToMem:
608 return "RegToMemSpillCopy";
609 case MemToReg:
610 return "MemToRegSpillCopy";
611 case PhiLocationDifferToInputLocation:
612 return "PhiLocationDifferToInputLocationSpillCopy";
613 case BasePointerToMem:
614 return "BasePointerToMemSpillCopy";
615 case InputToRematerialization:
616 return "InputToRematerializationSpillCopy";
617 case CallUse:
618 return "CallUseSpillCopy";
619 case Bound:
620 return "BoundSpillCopy";
621 default:
622 assert(false, "Must have valid spill type");
623 return "MachSpillCopy";
624 }
625 }
626
627 virtual const char *Name() const {
628 return spill_type(_spill_type);
629 }
630
631 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
632 #endif
633 };
634
635 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
636 // however it doesn't have a control input and is more like a MergeMem.
637 // It is inserted after the register allocation is done to ensure that nodes use single
638 // definition of a multidef lrg in a block.
639 class MachMergeNode : public MachIdealNode {
640 public:
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543 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
544 // location (stack or register).
545 class MachSpillCopyNode : public MachIdealNode {
546 public:
547 enum SpillType {
548 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
549 PhiInput, // Inserted when coalescing of a phi node and its input fails
550 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
551 LoopPhiInput, // Pre-split compares of loop-phis
552 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
553 // if in high pressure region or the lrg is bound
554 RegToReg, // A register to register move
555 RegToMem, // A register to memory move
556 MemToReg, // A memory to register move
557 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
558 // the phi and its input resides at different locations (i.e. reg or mem)
559 BasePointerToMem, // Spill base pointer to memory at safepoint
560 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
561 // stretched beyond a new definition point, therefore we split out new copies instead
562 CallUse, // Spill use at a call
563 Bound, // An lrg marked as spill that is bound and needs to be spilled at a use
564 Pair // Spill two in a pair
565 };
566 private:
567 const RegMask *_in; // RegMask for input
568 const RegMask *_out; // RegMask for output
569 const Type *_type;
570 SpillType _spill_type;
571 OptoReg::Name pair_hi_reg; // Ugly prototype
572 public:
573 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
574 MachIdealNode(), _spill_type(spill_type), _in(&in), _out(&out), _type(n->bottom_type()) {
575 init_class_id(Class_MachSpillCopy);
576 init_flags(Flag_is_Copy);
577 add_req(NULL);
578 add_req(n);
579 pair_hi_reg = OptoReg::Bad;
580 }
581 virtual uint size_of() const { return sizeof(*this); }
582 void set_out_RegMask(const RegMask &out) { _out = &out; }
583 void set_in_RegMask(const RegMask &in) { _in = ∈ }
584 virtual const RegMask &out_RegMask() const { return *_out; }
585 virtual const RegMask &in_RegMask(uint) const { return *_in; }
586 virtual const class Type *bottom_type() const { return _type; }
587 virtual uint ideal_reg() const { return _type->ideal_reg(); }
588 virtual uint oper_input_base() const { return 1; }
589 uint implementation( CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
590
591 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const;
592 virtual uint size(PhaseRegAlloc *ra_) const;
593 #ifdef AARCH64
594 virtual MachNode *peephole(Block *block, int block_index, PhaseRegAlloc *ra_, int &deleted);
595 #endif
596
597 #ifndef PRODUCT
598 static const char *spill_type(SpillType st) {
599 switch (st) {
600 case TwoAddress:
601 return "TwoAddressSpillCopy";
602 case PhiInput:
603 return "PhiInputSpillCopy";
604 case DebugUse:
605 return "DebugUseSpillCopy";
606 case LoopPhiInput:
607 return "LoopPhiInputSpillCopy";
608 case Definition:
609 return "DefinitionSpillCopy";
610 case RegToReg:
611 return "RegToRegSpillCopy";
612 case RegToMem:
613 return "RegToMemSpillCopy";
614 case MemToReg:
615 return "MemToRegSpillCopy";
616 case PhiLocationDifferToInputLocation:
617 return "PhiLocationDifferToInputLocationSpillCopy";
618 case BasePointerToMem:
619 return "BasePointerToMemSpillCopy";
620 case InputToRematerialization:
621 return "InputToRematerializationSpillCopy";
622 case CallUse:
623 return "CallUseSpillCopy";
624 case Bound:
625 return "BoundSpillCopy";
626 case Pair:
627 return "Pair";
628 default:
629 assert(false, "Must have valid spill type");
630 return "MachSpillCopy";
631 }
632 }
633
634 virtual const char *Name() const {
635 return spill_type(_spill_type);
636 }
637
638 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
639 #endif
640 };
641
642 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
643 // however it doesn't have a control input and is more like a MergeMem.
644 // It is inserted after the register allocation is done to ensure that nodes use single
645 // definition of a multidef lrg in a block.
646 class MachMergeNode : public MachIdealNode {
647 public:
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