2409     if (failing()) {
2410       return;
2411     }
2412   }
2413 
2414   // Prior to register allocation we kept empty basic blocks in case the
2415   // the allocator needed a place to spill.  After register allocation we
2416   // are not adding any new instructions.  If any basic block is empty, we
2417   // can now safely remove it.
2418   {
2419     TracePhase tp("blockOrdering", &timers[_t_blockOrdering]);
2420     cfg.remove_empty_blocks();
2421     if (do_freq_based_layout()) {
2422       PhaseBlockLayout layout(cfg);
2423     } else {
2424       cfg.set_loop_alignment();
2425     }
2426     cfg.fixup_flow();
2427   }
2428 

2429   // Apply peephole optimizations
2430   if( OptoPeephole ) {
2431     TracePhase tp("peephole", &timers[_t_peephole]);
2432     PhasePeephole peep( _regalloc, cfg);
2433     peep.do_transform();
2434   }
2435 
2436   // Do late expand if CPU requires this.
2437   if (Matcher::require_postalloc_expand) {
2438     TracePhase tp("postalloc_expand", &timers[_t_postalloc_expand]);
2439     cfg.postalloc_expand(_regalloc);
2440   }
2441 
2442   // Convert Nodes to instruction bits in a buffer
2443   {
2444     TraceTime tp("output", &timers[_t_output], CITime);
2445     Output();
2446   }
2447 
2448   print_method(PHASE_FINAL_CODE);
2449 
2450   // He's dead, Jim.
2451   _cfg     = (PhaseCFG*)0xdeadbeef;
2452   _regalloc = (PhaseChaitin*)0xdeadbeef;
2453 }
2454 
2455 

2409     if (failing()) {
2410       return;
2411     }
2412   }
2413 
2414   // Prior to register allocation we kept empty basic blocks in case the
2415   // the allocator needed a place to spill.  After register allocation we
2416   // are not adding any new instructions.  If any basic block is empty, we
2417   // can now safely remove it.
2418   {
2419     TracePhase tp("blockOrdering", &timers[_t_blockOrdering]);
2420     cfg.remove_empty_blocks();
2421     if (do_freq_based_layout()) {
2422       PhaseBlockLayout layout(cfg);
2423     } else {
2424       cfg.set_loop_alignment();
2425     }
2426     cfg.fixup_flow();
2427   }
2428 
2429 #if 0
2430   // Apply peephole optimizations
2431   if( OptoPeephole ) {
2432     TracePhase tp("peephole", &timers[_t_peephole]);
2433     PhasePeephole peep( _regalloc, cfg);
2434     peep.do_transform();
2435   }
2436 #endif
2437   // Do late expand if CPU requires this.
2438   if (Matcher::require_postalloc_expand) {
2439     TracePhase tp("postalloc_expand", &timers[_t_postalloc_expand]);
2440     cfg.postalloc_expand(_regalloc);
2441   }
2442 
2443   // Convert Nodes to instruction bits in a buffer
2444   {
2445     TraceTime tp("output", &timers[_t_output], CITime);
2446     Output();
2447   }
2448 
2449   print_method(PHASE_FINAL_CODE);
2450 
2451   // He's dead, Jim.
2452   _cfg     = (PhaseCFG*)0xdeadbeef;
2453   _regalloc = (PhaseChaitin*)0xdeadbeef;
2454 }
2455 
2456