1 /*
2 * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_OPTO_REGMASK_HPP
26 #define SHARE_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "opto/optoreg.hpp"
30 #include "utilities/count_leading_zeros.hpp"
31 #include "utilities/count_trailing_zeros.hpp"
32
33 //-------------Non-zero bit search methods used by RegMask---------------------
34 // Find lowest 1, undefined if empty/0
35 static int find_lowest_bit(uint32_t mask) {
36 return count_trailing_zeros(mask);
37 }
38 // Find highest 1, undefined if empty/0
39 static int find_highest_bit(uint32_t mask) {
40 return count_leading_zeros(mask) ^ 31;
41 }
42
43 //------------------------------RegMask----------------------------------------
44 // The ADL file describes how to print the machine-specific registers, as well
45 // as any notion of register classes. We provide a register mask, which is
46 // just a collection of Register numbers.
47
48 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
49 // RM_SIZE is the size of a register mask in words.
50 // FORALL_BODY replicates a BODY macro once per word in the register mask.
51 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
52 // However, it means the ADLC can redefine the unroll macro and all loops
74 _LogWordBits = LogBitsPerInt,
75 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
76 };
77
78 public:
79 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
80
81 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
82 // Also, consider the maximum alignment size for a normally allocated
83 // value. Since we allocate register pairs but not register quads (at
84 // present), this alignment is SlotsPerLong (== 2). A normally
85 // aligned allocated register is either a single register, or a pair
86 // of adjacent registers, the lower-numbered being even.
87 // See also is_aligned_Pairs() below, and the padding added before
88 // Matcher::_new_SP to keep allocated pairs aligned properly.
89 // If we ever go to quad-word allocations, SlotsPerQuad will become
90 // the controlling alignment constraint. Note that this alignment
91 // requirement is internal to the allocator, and independent of any
92 // particular platform.
93 enum { SlotsPerLong = 2,
94 SlotsPerVecS = 1,
95 SlotsPerVecD = 2,
96 SlotsPerVecX = 4,
97 SlotsPerVecY = 8,
98 SlotsPerVecZ = 16 };
99
100 // A constructor only used by the ADLC output. All mask fields are filled
101 // in directly. Calls to this look something like RM(1,2,3,4);
102 RegMask(
103 # define BODY(I) int a##I,
104 FORALL_BODY
105 # undef BODY
106 int dummy = 0) {
107 # define BODY(I) _A[I] = a##I;
108 FORALL_BODY
109 # undef BODY
110 _lwm = 0;
111 _hwm = RM_SIZE - 1;
112 while (_hwm > 0 && _A[_hwm] == 0) _hwm--;
113 while ((_lwm < _hwm) && _A[_lwm] == 0) _lwm++;
114 assert(valid_watermarks(), "post-condition");
115 }
116
117 // Handy copying constructor
118 RegMask(RegMask *rm) {
202 }
203 for (int i = _hwm + 1; i < RM_SIZE; i++) {
204 assert(_A[i] == 0, "_hwm too low: %d regs at: %d", _hwm, i);
205 }
206 return true;
207 }
208 #endif // !ASSERT
209
210 // Test that the mask contains only aligned adjacent bit pairs
211 bool is_aligned_pairs() const;
212
213 // mask is a pair of misaligned registers
214 bool is_misaligned_pair() const;
215 // Test for single register
216 bool is_bound1() const;
217 // Test for a single adjacent pair
218 bool is_bound_pair() const;
219 // Test for a single adjacent set of ideal register's size.
220 bool is_bound(uint ireg) const;
221
222 // Find the lowest-numbered register set in the mask. Return the
223 // HIGHEST register number in the set, or BAD if no sets.
224 // Assert that the mask contains only bit sets.
225 OptoReg::Name find_first_set(const int size) const;
226
227 // Clear out partial bits; leave only aligned adjacent bit sets of size.
228 void clear_to_sets(const int size);
229 // Smear out partial bits to aligned adjacent bit sets.
230 void smear_to_sets(const int size);
231 // Test that the mask contains only aligned adjacent bit sets
232 bool is_aligned_sets(const int size) const;
233
234 // Test for a single adjacent set
235 int is_bound_set(const int size) const;
236
237 static bool is_vector(uint ireg);
238 static int num_registers(uint ireg);
239
240 // Fast overlap test. Non-zero if any registers in common.
241 int overlap(const RegMask &rm) const {
242 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
243 int hwm = MIN2(_hwm, rm._hwm);
244 int lwm = MAX2(_lwm, rm._lwm);
245 int result = 0;
246 for (int i = lwm; i <= hwm; i++) {
247 result |= _A[i] & rm._A[i];
248 }
249 return result;
250 }
251
252 // Special test for register pressure based splitting
253 // UP means register only, Register plus stack, or stack only is DOWN
254 bool is_UP() const;
255
256 // Clear a register mask
257 void Clear() {
258 _lwm = RM_SIZE - 1;
|
1 /*
2 * Copyright (c) 1997, 2020, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef SHARE_OPTO_REGMASK_HPP
26 #define SHARE_OPTO_REGMASK_HPP
27
28 #include "code/vmreg.hpp"
29 #include "opto/optoreg.hpp"
30 #include "utilities/count_leading_zeros.hpp"
31 #include "utilities/count_trailing_zeros.hpp"
32
33 class LRG;
34
35 //-------------Non-zero bit search methods used by RegMask---------------------
36 // Find lowest 1, undefined if empty/0
37 static int find_lowest_bit(uint32_t mask) {
38 return count_trailing_zeros(mask);
39 }
40 // Find highest 1, undefined if empty/0
41 static int find_highest_bit(uint32_t mask) {
42 return count_leading_zeros(mask) ^ 31;
43 }
44
45 //------------------------------RegMask----------------------------------------
46 // The ADL file describes how to print the machine-specific registers, as well
47 // as any notion of register classes. We provide a register mask, which is
48 // just a collection of Register numbers.
49
50 // The ADLC defines 2 macros, RM_SIZE and FORALL_BODY.
51 // RM_SIZE is the size of a register mask in words.
52 // FORALL_BODY replicates a BODY macro once per word in the register mask.
53 // The usage is somewhat clumsy and limited to the regmask.[h,c]pp files.
54 // However, it means the ADLC can redefine the unroll macro and all loops
76 _LogWordBits = LogBitsPerInt,
77 _RM_SIZE = RM_SIZE // local constant, imported, then hidden by #undef
78 };
79
80 public:
81 enum { CHUNK_SIZE = RM_SIZE*_WordBits };
82
83 // SlotsPerLong is 2, since slots are 32 bits and longs are 64 bits.
84 // Also, consider the maximum alignment size for a normally allocated
85 // value. Since we allocate register pairs but not register quads (at
86 // present), this alignment is SlotsPerLong (== 2). A normally
87 // aligned allocated register is either a single register, or a pair
88 // of adjacent registers, the lower-numbered being even.
89 // See also is_aligned_Pairs() below, and the padding added before
90 // Matcher::_new_SP to keep allocated pairs aligned properly.
91 // If we ever go to quad-word allocations, SlotsPerQuad will become
92 // the controlling alignment constraint. Note that this alignment
93 // requirement is internal to the allocator, and independent of any
94 // particular platform.
95 enum { SlotsPerLong = 2,
96 SlotsPerVecA = 8,
97 SlotsPerVecS = 1,
98 SlotsPerVecD = 2,
99 SlotsPerVecX = 4,
100 SlotsPerVecY = 8,
101 SlotsPerVecZ = 16,
102 };
103
104 // A constructor only used by the ADLC output. All mask fields are filled
105 // in directly. Calls to this look something like RM(1,2,3,4);
106 RegMask(
107 # define BODY(I) int a##I,
108 FORALL_BODY
109 # undef BODY
110 int dummy = 0) {
111 # define BODY(I) _A[I] = a##I;
112 FORALL_BODY
113 # undef BODY
114 _lwm = 0;
115 _hwm = RM_SIZE - 1;
116 while (_hwm > 0 && _A[_hwm] == 0) _hwm--;
117 while ((_lwm < _hwm) && _A[_lwm] == 0) _lwm++;
118 assert(valid_watermarks(), "post-condition");
119 }
120
121 // Handy copying constructor
122 RegMask(RegMask *rm) {
206 }
207 for (int i = _hwm + 1; i < RM_SIZE; i++) {
208 assert(_A[i] == 0, "_hwm too low: %d regs at: %d", _hwm, i);
209 }
210 return true;
211 }
212 #endif // !ASSERT
213
214 // Test that the mask contains only aligned adjacent bit pairs
215 bool is_aligned_pairs() const;
216
217 // mask is a pair of misaligned registers
218 bool is_misaligned_pair() const;
219 // Test for single register
220 bool is_bound1() const;
221 // Test for a single adjacent pair
222 bool is_bound_pair() const;
223 // Test for a single adjacent set of ideal register's size.
224 bool is_bound(uint ireg) const;
225
226 // Check that whether given reg number with size is valid
227 // for current regmask, where reg is the highest number.
228 bool is_valid_reg(OptoReg::Name reg, const int size) const;
229
230 // Find the lowest-numbered register set in the mask. Return the
231 // HIGHEST register number in the set, or BAD if no sets.
232 // Assert that the mask contains only bit sets.
233 OptoReg::Name find_first_set(LRG &lrg, const int size) const;
234
235 // Clear out partial bits; leave only aligned adjacent bit sets of size.
236 void clear_to_sets(const int size);
237 // Smear out partial bits to aligned adjacent bit sets.
238 void smear_to_sets(const int size);
239 // Test that the mask contains only aligned adjacent bit sets
240 bool is_aligned_sets(const int size) const;
241
242 // Test for a single adjacent set
243 int is_bound_set(const int size) const;
244
245 static bool is_vector(uint ireg);
246 static int num_registers(uint ireg);
247 static int num_registers(uint ireg, LRG &lrg);
248
249 // Fast overlap test. Non-zero if any registers in common.
250 int overlap(const RegMask &rm) const {
251 assert(valid_watermarks() && rm.valid_watermarks(), "sanity");
252 int hwm = MIN2(_hwm, rm._hwm);
253 int lwm = MAX2(_lwm, rm._lwm);
254 int result = 0;
255 for (int i = lwm; i <= hwm; i++) {
256 result |= _A[i] & rm._A[i];
257 }
258 return result;
259 }
260
261 // Special test for register pressure based splitting
262 // UP means register only, Register plus stack, or stack only is DOWN
263 bool is_UP() const;
264
265 // Clear a register mask
266 void Clear() {
267 _lwm = RM_SIZE - 1;
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