51 // associated with instructions preceding isync have
52 // been performed.
53 //
54 // Semantic barrier instructions:
55 // (as defined in orderAccess.hpp)
56 //
57 // - release orders Store|Store, (maps to lwsync)
58 // Load|Store
59 // - acquire orders Load|Store, (maps to lwsync)
60 // Load|Load
61 // - fence orders Store|Store, (maps to sync)
62 // Load|Store,
63 // Load|Load,
64 // Store|Load
65 //
66
67 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
68 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
69 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
70 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
71 // Use twi-isync for load_acquire (faster than lwsync).
72 #define inlasm_acquire_reg(X) __asm__ __volatile__ ("twi 0,%0,0\n isync\n" : : "r" (X) : "memory");
73
74 inline void OrderAccess::loadload() { inlasm_lwsync(); }
75 inline void OrderAccess::storestore() { inlasm_lwsync(); }
76 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
77 inline void OrderAccess::storeload() { inlasm_sync(); }
78
79 inline void OrderAccess::acquire() { inlasm_lwsync(); }
80 inline void OrderAccess::release() { inlasm_lwsync(); }
81 inline void OrderAccess::fence() { inlasm_sync(); }
82 inline void OrderAccess::cross_modify_fence()
83 { inlasm_isync(); }
84
85 template<size_t byte_size>
86 struct OrderAccess::PlatformOrderedLoad<byte_size, X_ACQUIRE>
87 {
88 template <typename T>
89 T operator()(const volatile T* p) const { T t = Atomic::load(p); inlasm_acquire_reg(t); return t; }
90 };
91
92 #undef inlasm_sync
93 #undef inlasm_lwsync
94 #undef inlasm_eieio
95 #undef inlasm_isync
96 #undef inlasm_acquire_reg
97
98 #endif // OS_CPU_LINUX_PPC_ORDERACCESS_LINUX_PPC_HPP
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51 // associated with instructions preceding isync have
52 // been performed.
53 //
54 // Semantic barrier instructions:
55 // (as defined in orderAccess.hpp)
56 //
57 // - release orders Store|Store, (maps to lwsync)
58 // Load|Store
59 // - acquire orders Load|Store, (maps to lwsync)
60 // Load|Load
61 // - fence orders Store|Store, (maps to sync)
62 // Load|Store,
63 // Load|Load,
64 // Store|Load
65 //
66
67 #define inlasm_sync() __asm__ __volatile__ ("sync" : : : "memory");
68 #define inlasm_lwsync() __asm__ __volatile__ ("lwsync" : : : "memory");
69 #define inlasm_eieio() __asm__ __volatile__ ("eieio" : : : "memory");
70 #define inlasm_isync() __asm__ __volatile__ ("isync" : : : "memory");
71
72 inline void OrderAccess::loadload() { inlasm_lwsync(); }
73 inline void OrderAccess::storestore() { inlasm_lwsync(); }
74 inline void OrderAccess::loadstore() { inlasm_lwsync(); }
75 inline void OrderAccess::storeload() { inlasm_sync(); }
76
77 inline void OrderAccess::acquire() { inlasm_lwsync(); }
78 inline void OrderAccess::release() { inlasm_lwsync(); }
79 inline void OrderAccess::fence() { inlasm_sync(); }
80 inline void OrderAccess::cross_modify_fence()
81 { inlasm_isync(); }
82
83 #undef inlasm_sync
84 #undef inlasm_lwsync
85 #undef inlasm_eieio
86 #undef inlasm_isync
87
88 #endif // OS_CPU_LINUX_PPC_ORDERACCESS_LINUX_PPC_HPP
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