73 : _compilation(ir->compilation())
74 , _ir(ir)
75 , _gen(gen)
76 , _frame_map(frame_map)
77 , _cached_blocks(*ir->linear_scan_order())
78 , _num_virtual_regs(gen->max_virtual_register_number())
79 , _has_fpu_registers(false)
80 , _num_calls(-1)
81 , _max_spills(0)
82 , _unused_spill_slot(-1)
83 , _intervals(0) // initialized later with correct length
84 , _new_intervals_from_allocation(NULL)
85 , _sorted_intervals(NULL)
86 , _needs_full_resort(false)
87 , _lir_ops(0) // initialized later with correct length
88 , _block_of_op(0) // initialized later with correct length
89 , _has_info(0)
90 , _has_call(0)
91 , _interval_in_loop(0) // initialized later with correct length
92 , _scope_value_cache(0) // initialized later with correct length
93 #ifdef X86
94 , _fpu_stack_allocator(NULL)
95 #endif
96 {
97 assert(this->ir() != NULL, "check if valid");
98 assert(this->compilation() != NULL, "check if valid");
99 assert(this->gen() != NULL, "check if valid");
100 assert(this->frame_map() != NULL, "check if valid");
101 }
102
103
104 // ********** functions for converting LIR-Operands to register numbers
105 //
106 // Emulate a flat register file comprising physical integer registers,
107 // physical floating-point registers and virtual registers, in that order.
108 // Virtual registers already have appropriate numbers, since V0 is
109 // the number of physical registers.
110 // Returns -1 for hi word if opr is a single word operand.
111 //
112 // Note: the inverse operation (calculating an operand for register numbers)
113 // is done in calc_operand_for_interval()
2636 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2637 _scope_value_cache.at_put(cache_idx, sv);
2638 }
2639
2640 // check if cached value is correct
2641 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2642
2643 scope_values->append(sv);
2644 return 1;
2645
2646 #ifdef X86
2647 } else if (opr->is_single_xmm()) {
2648 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2649 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2650
2651 scope_values->append(sv);
2652 return 1;
2653 #endif
2654
2655 } else if (opr->is_single_fpu()) {
2656 #ifdef X86
2657 // the exact location of fpu stack values is only known
2658 // during fpu stack allocation, so the stack allocator object
2659 // must be present
2660 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2661 assert(_fpu_stack_allocator != NULL, "must be present");
2662 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2663 #endif
2664
2665 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2666 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2667 #ifndef __SOFTFP__
2668 #ifndef VM_LITTLE_ENDIAN
2669 // On S390 a (single precision) float value occupies only the high
2670 // word of the full double register. So when the double register is
2671 // stored to memory (e.g. by the RegisterSaver), then the float value
2672 // is found at offset 0. I.e. the code below is not needed on S390.
2673 #ifndef S390
2674 if (! float_saved_as_double) {
2675 // On big endian system, we may have an issue if float registers use only
2676 // the low half of the (same) double registers.
2677 // Both the float and the double could have the same regnr but would correspond
2678 // to two different addresses once saved.
2679
2680 // get next safely (no assertion checks)
2681 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2682 if (next->is_reg() &&
2747 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2748 second = _int_0_scope_value;
2749 # else
2750 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2751 // %%% This is probably a waste but we'll keep things as they were for now
2752 if (true) {
2753 VMReg rname_second = rname_first->next();
2754 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2755 }
2756 # endif
2757 #endif
2758
2759 } else if (opr->is_double_fpu()) {
2760 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2761 // the double as float registers in the native ordering. On X86,
2762 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2763 // the low-order word of the double and fpu_regnrLo + 1 is the
2764 // name for the other half. *first and *second must represent the
2765 // least and most significant words, respectively.
2766
2767 #ifdef X86
2768 // the exact location of fpu stack values is only known
2769 // during fpu stack allocation, so the stack allocator object
2770 // must be present
2771 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2772 assert(_fpu_stack_allocator != NULL, "must be present");
2773 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2774
2775 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2776 #endif
2777 #ifdef SPARC
2778 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2779 #endif
2780 #ifdef ARM32
2781 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2782 #endif
2783 #ifdef PPC32
2784 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2785 #endif
2786
2787 #ifdef VM_LITTLE_ENDIAN
2788 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2789 #else
2790 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2791 #endif
2792
2793 #ifdef _LP64
2794 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2795 second = _int_0_scope_value;
2796 #else
|
73 : _compilation(ir->compilation())
74 , _ir(ir)
75 , _gen(gen)
76 , _frame_map(frame_map)
77 , _cached_blocks(*ir->linear_scan_order())
78 , _num_virtual_regs(gen->max_virtual_register_number())
79 , _has_fpu_registers(false)
80 , _num_calls(-1)
81 , _max_spills(0)
82 , _unused_spill_slot(-1)
83 , _intervals(0) // initialized later with correct length
84 , _new_intervals_from_allocation(NULL)
85 , _sorted_intervals(NULL)
86 , _needs_full_resort(false)
87 , _lir_ops(0) // initialized later with correct length
88 , _block_of_op(0) // initialized later with correct length
89 , _has_info(0)
90 , _has_call(0)
91 , _interval_in_loop(0) // initialized later with correct length
92 , _scope_value_cache(0) // initialized later with correct length
93 #ifdef IA32
94 , _fpu_stack_allocator(NULL)
95 #endif
96 {
97 assert(this->ir() != NULL, "check if valid");
98 assert(this->compilation() != NULL, "check if valid");
99 assert(this->gen() != NULL, "check if valid");
100 assert(this->frame_map() != NULL, "check if valid");
101 }
102
103
104 // ********** functions for converting LIR-Operands to register numbers
105 //
106 // Emulate a flat register file comprising physical integer registers,
107 // physical floating-point registers and virtual registers, in that order.
108 // Virtual registers already have appropriate numbers, since V0 is
109 // the number of physical registers.
110 // Returns -1 for hi word if opr is a single word operand.
111 //
112 // Note: the inverse operation (calculating an operand for register numbers)
113 // is done in calc_operand_for_interval()
2636 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2637 _scope_value_cache.at_put(cache_idx, sv);
2638 }
2639
2640 // check if cached value is correct
2641 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2642
2643 scope_values->append(sv);
2644 return 1;
2645
2646 #ifdef X86
2647 } else if (opr->is_single_xmm()) {
2648 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2649 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2650
2651 scope_values->append(sv);
2652 return 1;
2653 #endif
2654
2655 } else if (opr->is_single_fpu()) {
2656 #ifdef IA32
2657 // the exact location of fpu stack values is only known
2658 // during fpu stack allocation, so the stack allocator object
2659 // must be present
2660 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2661 assert(_fpu_stack_allocator != NULL, "must be present");
2662 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2663 #elif defined(IA64)
2664 assert(false, "FPU not used on x86-64");
2665 #endif
2666
2667 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2668 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2669 #ifndef __SOFTFP__
2670 #ifndef VM_LITTLE_ENDIAN
2671 // On S390 a (single precision) float value occupies only the high
2672 // word of the full double register. So when the double register is
2673 // stored to memory (e.g. by the RegisterSaver), then the float value
2674 // is found at offset 0. I.e. the code below is not needed on S390.
2675 #ifndef S390
2676 if (! float_saved_as_double) {
2677 // On big endian system, we may have an issue if float registers use only
2678 // the low half of the (same) double registers.
2679 // Both the float and the double could have the same regnr but would correspond
2680 // to two different addresses once saved.
2681
2682 // get next safely (no assertion checks)
2683 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2684 if (next->is_reg() &&
2749 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2750 second = _int_0_scope_value;
2751 # else
2752 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2753 // %%% This is probably a waste but we'll keep things as they were for now
2754 if (true) {
2755 VMReg rname_second = rname_first->next();
2756 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2757 }
2758 # endif
2759 #endif
2760
2761 } else if (opr->is_double_fpu()) {
2762 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2763 // the double as float registers in the native ordering. On X86,
2764 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2765 // the low-order word of the double and fpu_regnrLo + 1 is the
2766 // name for the other half. *first and *second must represent the
2767 // least and most significant words, respectively.
2768
2769 #ifdef IA32
2770 // the exact location of fpu stack values is only known
2771 // during fpu stack allocation, so the stack allocator object
2772 // must be present
2773 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2774 assert(_fpu_stack_allocator != NULL, "must be present");
2775 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2776
2777 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2778 #endif
2779 #ifdef IA64
2780 assert(false, "FPU not used on x86-64");
2781 #endif
2782 #ifdef SPARC
2783 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi() + 1, "assumed in calculation (only fpu_regnrHi is used)");
2784 #endif
2785 #ifdef ARM32
2786 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2787 #endif
2788 #ifdef PPC32
2789 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2790 #endif
2791
2792 #ifdef VM_LITTLE_ENDIAN
2793 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2794 #else
2795 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2796 #endif
2797
2798 #ifdef _LP64
2799 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2800 second = _int_0_scope_value;
2801 #else
|