26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [Op_RegI] = NULL;
78 idealreg2spillmask [Op_RegN] = NULL;
79 idealreg2spillmask [Op_RegL] = NULL;
80 idealreg2spillmask [Op_RegF] = NULL;
81 idealreg2spillmask [Op_RegD] = NULL;
82 idealreg2spillmask [Op_RegP] = NULL;
83 idealreg2spillmask [Op_VecS] = NULL;
84 idealreg2spillmask [Op_VecD] = NULL;
85 idealreg2spillmask [Op_VecX] = NULL;
86 idealreg2spillmask [Op_VecY] = NULL;
87 idealreg2spillmask [Op_VecZ] = NULL;
88
89 idealreg2debugmask [Op_RegI] = NULL;
90 idealreg2debugmask [Op_RegN] = NULL;
91 idealreg2debugmask [Op_RegL] = NULL;
92 idealreg2debugmask [Op_RegF] = NULL;
93 idealreg2debugmask [Op_RegD] = NULL;
94 idealreg2debugmask [Op_RegP] = NULL;
95 idealreg2debugmask [Op_VecS] = NULL;
96 idealreg2debugmask [Op_VecD] = NULL;
97 idealreg2debugmask [Op_VecX] = NULL;
98 idealreg2debugmask [Op_VecY] = NULL;
99 idealreg2debugmask [Op_VecZ] = NULL;
100
101 idealreg2mhdebugmask[Op_RegI] = NULL;
102 idealreg2mhdebugmask[Op_RegN] = NULL;
103 idealreg2mhdebugmask[Op_RegL] = NULL;
104 idealreg2mhdebugmask[Op_RegF] = NULL;
105 idealreg2mhdebugmask[Op_RegD] = NULL;
106 idealreg2mhdebugmask[Op_RegP] = NULL;
107 idealreg2mhdebugmask[Op_VecS] = NULL;
108 idealreg2mhdebugmask[Op_VecD] = NULL;
109 idealreg2mhdebugmask[Op_VecX] = NULL;
110 idealreg2mhdebugmask[Op_VecY] = NULL;
111 idealreg2mhdebugmask[Op_VecZ] = NULL;
112
113 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
114 }
115
116 //------------------------------warp_incoming_stk_arg------------------------
117 // This warps a VMReg into an OptoReg::Name
118 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
119 OptoReg::Name warped;
120 if( reg->is_stack() ) { // Stack slot argument?
121 warped = OptoReg::add(_old_SP, reg->reg2stack() );
122 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
123 if( warped >= _in_arg_limit )
124 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
125 if (!RegMask::can_represent_arg(warped)) {
126 // the compiler cannot represent this method's calling sequence
127 C->record_method_not_compilable("unsupported incoming calling sequence");
128 return OptoReg::Bad;
129 }
130 return warped;
131 }
168
169 //---------------------------match---------------------------------------------
170 void Matcher::match( ) {
171 if( MaxLabelRootDepth < 100 ) { // Too small?
172 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
173 MaxLabelRootDepth = 100;
174 }
175 // One-time initialization of some register masks.
176 init_spill_mask( C->root()->in(1) );
177 _return_addr_mask = return_addr();
178 #ifdef _LP64
179 // Pointers take 2 slots in 64-bit land
180 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
181 #endif
182
183 // Map a Java-signature return type into return register-value
184 // machine registers for 0, 1 and 2 returned values.
185 const TypeTuple *range = C->tf()->range();
186 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
187 // Get ideal-register return type
188 int ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
189 // Get machine return register
190 uint sop = C->start()->Opcode();
191 OptoRegPair regs = return_value(ireg, false);
192
193 // And mask for same
194 _return_value_mask = RegMask(regs.first());
195 if( OptoReg::is_valid(regs.second()) )
196 _return_value_mask.Insert(regs.second());
197 }
198
199 // ---------------
200 // Frame Layout
201
202 // Need the method signature to determine the incoming argument types,
203 // because the types determine which registers the incoming arguments are
204 // in, and this affects the matched code.
205 const TypeTuple *domain = C->tf()->domain();
206 uint argcnt = domain->cnt() - TypeFunc::Parms;
207 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
208 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
209 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
210 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
402 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
403 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
404 // Do all the pre-defined register masks
405 rms[TypeFunc::Control ] = RegMask::Empty;
406 rms[TypeFunc::I_O ] = RegMask::Empty;
407 rms[TypeFunc::Memory ] = RegMask::Empty;
408 rms[TypeFunc::ReturnAdr] = ret_adr;
409 rms[TypeFunc::FramePtr ] = fp;
410 return rms;
411 }
412
413 //---------------------------init_first_stack_mask-----------------------------
414 // Create the initial stack mask used by values spilling to the stack.
415 // Disallow any debug info in outgoing argument areas by setting the
416 // initial mask accordingly.
417 void Matcher::init_first_stack_mask() {
418
419 // Allocate storage for spill masks as masks for the appropriate load type.
420 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
421
422 idealreg2spillmask [Op_RegN] = &rms[0];
423 idealreg2spillmask [Op_RegI] = &rms[1];
424 idealreg2spillmask [Op_RegL] = &rms[2];
425 idealreg2spillmask [Op_RegF] = &rms[3];
426 idealreg2spillmask [Op_RegD] = &rms[4];
427 idealreg2spillmask [Op_RegP] = &rms[5];
428
429 idealreg2debugmask [Op_RegN] = &rms[6];
430 idealreg2debugmask [Op_RegI] = &rms[7];
431 idealreg2debugmask [Op_RegL] = &rms[8];
432 idealreg2debugmask [Op_RegF] = &rms[9];
433 idealreg2debugmask [Op_RegD] = &rms[10];
434 idealreg2debugmask [Op_RegP] = &rms[11];
435
436 idealreg2mhdebugmask[Op_RegN] = &rms[12];
437 idealreg2mhdebugmask[Op_RegI] = &rms[13];
438 idealreg2mhdebugmask[Op_RegL] = &rms[14];
439 idealreg2mhdebugmask[Op_RegF] = &rms[15];
440 idealreg2mhdebugmask[Op_RegD] = &rms[16];
441 idealreg2mhdebugmask[Op_RegP] = &rms[17];
442
443 idealreg2spillmask [Op_VecS] = &rms[18];
444 idealreg2spillmask [Op_VecD] = &rms[19];
445 idealreg2spillmask [Op_VecX] = &rms[20];
446 idealreg2spillmask [Op_VecY] = &rms[21];
447 idealreg2spillmask [Op_VecZ] = &rms[22];
448
449 OptoReg::Name i;
450
451 // At first, start with the empty mask
452 C->FIRST_STACK_mask().Clear();
453
454 // Add in the incoming argument area
455 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
456 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
457 C->FIRST_STACK_mask().Insert(i);
458 }
459 // Add in all bits past the outgoing argument area
460 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
461 "must be able to represent all call arguments in reg mask");
462 OptoReg::Name init = _out_arg_limit;
463 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
464 C->FIRST_STACK_mask().Insert(i);
465 }
466 // Finally, set the "infinite stack" bit.
467 C->FIRST_STACK_mask().set_AllStack();
468
469 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
470 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
471 // Keep spill masks aligned.
472 aligned_stack_mask.clear_to_pairs();
473 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
474
475 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
476 #ifdef _LP64
477 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
478 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
479 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
480 #else
481 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
482 #endif
483 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
484 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
486 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
487 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
488 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
489 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
490 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
491
492 if (Matcher::vector_size_supported(T_BYTE,4)) {
493 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
494 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
495 }
496 if (Matcher::vector_size_supported(T_FLOAT,2)) {
497 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
498 // RA guarantees such alignment since it is needed for Double and Long values.
499 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
500 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
501 }
502 if (Matcher::vector_size_supported(T_FLOAT,4)) {
503 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
504 //
505 // RA can use input arguments stack slots for spills but until RA
506 // we don't know frame size and offset of input arg stack slots.
507 //
508 // Exclude last input arg stack slots to avoid spilling vectors there
509 // otherwise vector spills could stomp over stack slots in caller frame.
510 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
511 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
512 aligned_stack_mask.Remove(in);
513 in = OptoReg::add(in, -1);
514 }
515 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
516 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
517 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
518 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
519 }
520 if (Matcher::vector_size_supported(T_FLOAT,8)) {
521 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
530 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,16)) {
533 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
542 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
550 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
551 #ifdef _LP64
552 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
553 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
554 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
555 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
556 #else
557 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
562 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [Op_RegN]= *idealreg2spillmask[Op_RegN];
571 *idealreg2debugmask [Op_RegI]= *idealreg2spillmask[Op_RegI];
572 *idealreg2debugmask [Op_RegL]= *idealreg2spillmask[Op_RegL];
573 *idealreg2debugmask [Op_RegF]= *idealreg2spillmask[Op_RegF];
574 *idealreg2debugmask [Op_RegD]= *idealreg2spillmask[Op_RegD];
575 *idealreg2debugmask [Op_RegP]= *idealreg2spillmask[Op_RegP];
576
577 *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
578 *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
579 *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
580 *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
581 *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
582 *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [Op_RegN]->Remove(i);
594 idealreg2debugmask [Op_RegI]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [Op_RegL]->Remove(i); // registers from debug
596 idealreg2debugmask [Op_RegF]->Remove(i); // masks
597 idealreg2debugmask [Op_RegD]->Remove(i);
598 idealreg2debugmask [Op_RegP]->Remove(i);
599
600 idealreg2mhdebugmask[Op_RegN]->Remove(i);
601 idealreg2mhdebugmask[Op_RegI]->Remove(i);
602 idealreg2mhdebugmask[Op_RegL]->Remove(i);
603 idealreg2mhdebugmask[Op_RegF]->Remove(i);
604 idealreg2mhdebugmask[Op_RegD]->Remove(i);
605 idealreg2mhdebugmask[Op_RegP]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
665 #ifdef _LP64
666 // Need two slots for ptrs in 64-bit land
667 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
668 #endif
669 }
670
671 // Input RegMask array shared by all TailCalls
672 uint tail_call_edge_cnt = TypeFunc::Parms+2;
673 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674
675 // Input RegMask array shared by all TailJumps
676 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
677 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
678
679 // TailCalls have 2 returned values (target & moop), whose masks come
680 // from the usual MachNode/MachOper mechanism. Find a sample
681 // TailCall to extract these masks and put the correct masks into
682 // the tail_call_rms array.
683 for( i=1; i < root->req(); i++ ) {
684 MachReturnNode *m = root->in(i)->as_MachReturn();
685 if( m->ideal_Opcode() == Op_TailCall ) {
686 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
687 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
688 break;
689 }
690 }
691
692 // TailJumps have 2 returned values (target & ex_oop), whose masks come
693 // from the usual MachNode/MachOper mechanism. Find a sample
694 // TailJump to extract these masks and put the correct masks into
695 // the tail_jump_rms array.
696 for( i=1; i < root->req(); i++ ) {
697 MachReturnNode *m = root->in(i)->as_MachReturn();
698 if( m->ideal_Opcode() == Op_TailJump ) {
699 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
700 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
701 break;
702 }
703 }
704
705 // Input RegMask array shared by all Halts
706 uint halt_edge_cnt = TypeFunc::Parms;
707 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
708
709 // Capture the return input masks into each exit flavor
710 for( i=1; i < root->req(); i++ ) {
711 MachReturnNode *exit = root->in(i)->as_MachReturn();
712 switch( exit->ideal_Opcode() ) {
713 case Op_Return : exit->_in_rms = ret_rms; break;
714 case Op_Rethrow : exit->_in_rms = reth_rms; break;
715 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
716 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
717 case Op_Halt : exit->_in_rms = halt_rms; break;
718 default : ShouldNotReachHere();
719 }
720 }
721
722 // Next unused projection number from Start.
723 int proj_cnt = C->tf()->domain()->cnt();
724
725 // Do all the save-on-entry registers. Make projections from Start for
726 // them, and give them a use at the exit points. To the allocator, they
727 // look like incoming register arguments.
728 for( i = 0; i < _last_Mach_Reg; i++ ) {
729 if( is_save_on_entry(i) ) {
730
731 // Add the save-on-entry to the mask array
732 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
733 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
734 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
735 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
736 // Halts need the SOE registers, but only in the stack as debug info.
737 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
738 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
739
740 Node *mproj;
741
742 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
743 // into a single RegD.
744 if( (i&1) == 0 &&
745 _register_save_type[i ] == Op_RegF &&
746 _register_save_type[i+1] == Op_RegF &&
747 is_save_on_entry(i+1) ) {
748 // Add other bit for double
749 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
750 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
751 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
752 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
753 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
754 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
755 proj_cnt += 2; // Skip 2 for doubles
756 }
757 else if( (i&1) == 1 && // Else check for high half of double
758 _register_save_type[i-1] == Op_RegF &&
759 _register_save_type[i ] == Op_RegF &&
760 is_save_on_entry(i-1) ) {
761 ret_rms [ ret_edge_cnt] = RegMask::Empty;
762 reth_rms [ reth_edge_cnt] = RegMask::Empty;
763 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
764 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
765 halt_rms [ halt_edge_cnt] = RegMask::Empty;
766 mproj = C->top();
767 }
768 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
769 // into a single RegL.
770 else if( (i&1) == 0 &&
771 _register_save_type[i ] == Op_RegI &&
772 _register_save_type[i+1] == Op_RegI &&
773 is_save_on_entry(i+1) ) {
774 // Add other bit for long
775 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
776 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
777 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
778 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
779 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
780 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
781 proj_cnt += 2; // Skip 2 for longs
782 }
783 else if( (i&1) == 1 && // Else check for high half of long
784 _register_save_type[i-1] == Op_RegI &&
785 _register_save_type[i ] == Op_RegI &&
786 is_save_on_entry(i-1) ) {
787 ret_rms [ ret_edge_cnt] = RegMask::Empty;
788 reth_rms [ reth_edge_cnt] = RegMask::Empty;
789 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
790 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
791 halt_rms [ halt_edge_cnt] = RegMask::Empty;
792 mproj = C->top();
793 } else {
794 // Make a projection for it off the Start
795 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
796 }
797
798 ret_edge_cnt ++;
799 reth_edge_cnt ++;
800 tail_call_edge_cnt ++;
801 tail_jump_edge_cnt ++;
802 halt_edge_cnt ++;
803
804 // Add a use of the SOE register to all exit paths
805 for( uint j=1; j < root->req(); j++ )
806 root->in(j)->add_req(mproj);
807 } // End of if a save-on-entry register
808 } // End of for all machine registers
809 }
810
811 //------------------------------init_spill_mask--------------------------------
812 void Matcher::init_spill_mask( Node *ret ) {
813 if( idealreg2regmask[Op_RegI] ) return; // One time only init
814
815 OptoReg::c_frame_pointer = c_frame_pointer();
816 c_frame_ptr_mask = c_frame_pointer();
817 #ifdef _LP64
818 // pointers are twice as big
819 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
820 #endif
821
822 // Start at OptoReg::stack0()
823 STACK_ONLY_mask.Clear();
824 OptoReg::Name init = OptoReg::stack2reg(0);
825 // STACK_ONLY_mask is all stack bits
826 OptoReg::Name i;
827 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
828 STACK_ONLY_mask.Insert(i);
829 // Also set the "infinite stack" bit.
830 STACK_ONLY_mask.set_AllStack();
831
832 // Copy the register names over into the shared world
833 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
839 // Grab the Frame Pointer
840 Node *fp = ret->in(TypeFunc::FramePtr);
841 Node *mem = ret->in(TypeFunc::Memory);
842 const TypePtr* atp = TypePtr::BOTTOM;
843 // Share frame pointer while making spill ops
844 set_shared(fp);
845
846 // Compute generic short-offset Loads
847 #ifdef _LP64
848 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
849 #endif
850 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
851 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
852 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
853 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
854 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
855 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
856 spillD != NULL && spillP != NULL, "");
857 // Get the ADLC notion of the right regmask, for each basic type.
858 #ifdef _LP64
859 idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
860 #endif
861 idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
862 idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
863 idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
864 idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
865 idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
866
867 // Vector regmasks.
868 if (Matcher::vector_size_supported(T_BYTE,4)) {
869 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
870 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
871 idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
872 }
873 if (Matcher::vector_size_supported(T_FLOAT,2)) {
874 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
875 idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
876 }
877 if (Matcher::vector_size_supported(T_FLOAT,4)) {
878 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
879 idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
880 }
881 if (Matcher::vector_size_supported(T_FLOAT,8)) {
882 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
883 idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
884 }
885 if (Matcher::vector_size_supported(T_FLOAT,16)) {
886 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
887 idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
888 }
889 }
890
891 #ifdef ASSERT
892 static void match_alias_type(Compile* C, Node* n, Node* m) {
893 if (!VerifyAliases) return; // do not go looking for trouble by default
894 const TypePtr* nat = n->adr_type();
895 const TypePtr* mat = m->adr_type();
896 int nidx = C->get_alias_index(nat);
897 int midx = C->get_alias_index(mat);
898 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
899 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
900 for (uint i = 1; i < n->req(); i++) {
901 Node* n1 = n->in(i);
902 const TypePtr* n1at = n1->adr_type();
903 if (n1at != NULL) {
904 nat = n1at;
905 nidx = C->get_alias_index(n1at);
906 }
907 }
908 }
909 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
910 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
911 switch (n->Opcode()) {
912 case Op_PrefetchAllocation:
913 nidx = Compile::AliasIdxRaw;
914 nat = TypeRawPtr::BOTTOM;
915 break;
916 }
917 }
918 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
919 switch (n->Opcode()) {
920 case Op_ClearArray:
921 midx = Compile::AliasIdxRaw;
922 mat = TypeRawPtr::BOTTOM;
923 break;
924 }
925 }
926 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
927 switch (n->Opcode()) {
928 case Op_Return:
929 case Op_Rethrow:
930 case Op_Halt:
931 case Op_TailCall:
932 case Op_TailJump:
933 nidx = Compile::AliasIdxBot;
934 nat = TypePtr::BOTTOM;
935 break;
936 }
937 }
938 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
939 switch (n->Opcode()) {
940 case Op_StrComp:
941 case Op_StrEquals:
942 case Op_StrIndexOf:
943 case Op_StrIndexOfChar:
944 case Op_AryEq:
945 case Op_HasNegatives:
946 case Op_MemBarVolatile:
947 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
948 case Op_StrInflatedCopy:
949 case Op_StrCompressedCopy:
950 case Op_OnSpinWait:
951 case Op_EncodeISOArray:
952 nidx = Compile::AliasIdxTop;
953 nat = NULL;
954 break;
955 }
956 }
957 if (nidx != midx) {
958 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
959 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
960 n->dump();
961 m->dump();
962 }
963 assert(C->subsume_loads() && C->must_alias(nat, midx),
964 "must not lose alias info when matching");
965 }
966 }
967 #endif
968
969 //------------------------------xform------------------------------------------
970 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
971 // Node in new-space. Given a new-space Node, recursively walk his children.
1043 // Handle precedence edges for interior nodes
1044 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1045 Node *m = n->in(i);
1046 if (m == NULL || C->node_arena()->contains(m)) continue;
1047 n->rm_prec(i);
1048 // set -1 to call add_prec() instead of set_req() during Step1
1049 mstack.push(m, Visit, n, -1);
1050 }
1051
1052 // For constant debug info, I'd rather have unmatched constants.
1053 int cnt = n->req();
1054 JVMState* jvms = n->jvms();
1055 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1056
1057 // Now do only debug info. Clone constants rather than matching.
1058 // Constants are represented directly in the debug info without
1059 // the need for executable machine instructions.
1060 // Monitor boxes are also represented directly.
1061 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1062 Node *m = n->in(i); // Get input
1063 int op = m->Opcode();
1064 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1065 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1066 op == Op_ConF || op == Op_ConD || op == Op_ConL
1067 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1068 ) {
1069 m = m->clone();
1070 #ifdef ASSERT
1071 _new2old_map.map(m->_idx, n);
1072 #endif
1073 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1074 mstack.push(m->in(0), Visit, m, 0);
1075 } else {
1076 mstack.push(m, Visit, n, i);
1077 }
1078 }
1079
1080 // And now walk his children, and convert his inputs to new-space.
1081 for( ; i >= 0; --i ) { // For all normal inputs do
1082 Node *m = n->in(i); // Get input
1083 if(m != NULL)
1084 mstack.push(m, Visit, n, i);
1085 }
1086
1281 } // End of for all arguments
1282
1283 // Compute number of stack slots needed to restore stack in case of
1284 // Pascal-style argument popping.
1285 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1286 }
1287
1288 // Compute the max stack slot killed by any call. These will not be
1289 // available for debug info, and will be used to adjust FIRST_STACK_mask
1290 // after all call sites have been visited.
1291 if( _out_arg_limit < out_arg_limit_per_call)
1292 _out_arg_limit = out_arg_limit_per_call;
1293
1294 if (mcall) {
1295 // Kill the outgoing argument area, including any non-argument holes and
1296 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1297 // Since the max-per-method covers the max-per-call-site and debug info
1298 // is excluded on the max-per-method basis, debug info cannot land in
1299 // this killed area.
1300 uint r_cnt = mcall->tf()->range()->cnt();
1301 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1302 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1303 C->record_method_not_compilable("unsupported outgoing calling sequence");
1304 } else {
1305 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1306 proj->_rout.Insert(OptoReg::Name(i));
1307 }
1308 if (proj->_rout.is_NotEmpty()) {
1309 push_projection(proj);
1310 }
1311 }
1312 // Transfer the safepoint information from the call to the mcall
1313 // Move the JVMState list
1314 msfpt->set_jvms(sfpt->jvms());
1315 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1316 jvms->set_map(sfpt);
1317 }
1318
1319 // Debug inputs begin just after the last incoming parameter
1320 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1321 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1329 // ins are not complete then.
1330 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1331 if (msfpt->jvms() &&
1332 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1333 // We added an edge before jvms, so we must adapt the position of the ins.
1334 msfpt->jvms()->adapt_position(+1);
1335 }
1336 }
1337
1338 // Registers killed by the call are set in the local scheduling pass
1339 // of Global Code Motion.
1340 return msfpt;
1341 }
1342
1343 //---------------------------match_tree----------------------------------------
1344 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1345 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1346 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1347 // a Load's result RegMask for memoization in idealreg2regmask[]
1348 MachNode *Matcher::match_tree( const Node *n ) {
1349 assert( n->Opcode() != Op_Phi, "cannot match" );
1350 assert( !n->is_block_start(), "cannot match" );
1351 // Set the mark for all locally allocated State objects.
1352 // When this call returns, the _states_arena arena will be reset
1353 // freeing all State objects.
1354 ResourceMark rm( &_states_arena );
1355
1356 LabelRootDepth = 0;
1357
1358 // StoreNodes require their Memory input to match any LoadNodes
1359 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1360 #ifdef ASSERT
1361 Node* save_mem_node = _mem_node;
1362 _mem_node = n->is_Store() ? (Node*)n : NULL;
1363 #endif
1364 // State object for root node of match tree
1365 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1366 State *s = new (&_states_arena) State;
1367 s->_kids[0] = NULL;
1368 s->_kids[1] = NULL;
1369 s->_leaf = (Node*)n;
1908 BasicType sig_bt = T_OBJECT;
1909 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1910 // Return argument 0 register. In the LP64 build pointers
1911 // take 2 registers, but the VM wants only the 'main' name.
1912 return OptoReg::as_OptoReg(regs.first());
1913 }
1914
1915 // This function identifies sub-graphs in which a 'load' node is
1916 // input to two different nodes, and such that it can be matched
1917 // with BMI instructions like blsi, blsr, etc.
1918 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1919 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1920 // refers to the same node.
1921 #ifdef X86
1922 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1923 // This is a temporary solution until we make DAGs expressible in ADL.
1924 template<typename ConType>
1925 class FusedPatternMatcher {
1926 Node* _op1_node;
1927 Node* _mop_node;
1928 int _con_op;
1929
1930 static int match_next(Node* n, int next_op, int next_op_idx) {
1931 if (n->in(1) == NULL || n->in(2) == NULL) {
1932 return -1;
1933 }
1934
1935 if (next_op_idx == -1) { // n is commutative, try rotations
1936 if (n->in(1)->Opcode() == next_op) {
1937 return 1;
1938 } else if (n->in(2)->Opcode() == next_op) {
1939 return 2;
1940 }
1941 } else {
1942 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1943 if (n->in(next_op_idx)->Opcode() == next_op) {
1944 return next_op_idx;
1945 }
1946 }
1947 return -1;
1948 }
1949 public:
1950 FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
1951 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1952
1953 bool match(int op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1954 int op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1955 typename ConType::NativeType con_value) {
1956 if (_op1_node->Opcode() != op1) {
1957 return false;
1958 }
1959 if (_mop_node->outcnt() > 2) {
1960 return false;
1961 }
1962 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1963 if (op1_op2_idx == -1) {
1964 return false;
1965 }
1966 // Memory operation must be the other edge
1967 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1968
1969 // Check that the mop node is really what we want
1970 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1971 Node *op2_node = _op1_node->in(op1_op2_idx);
1972 if (op2_node->outcnt() > 1) {
1973 return false;
1974 }
1978 return false;
1979 }
1980 // Memory operation must be the other edge
1981 int op2_mop_idx = (op2_con_idx & 1) + 1;
1982 // Check that the memory operation is the same node
1983 if (op2_node->in(op2_mop_idx) == _mop_node) {
1984 // Now check the constant
1985 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1986 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1987 return true;
1988 }
1989 }
1990 }
1991 return false;
1992 }
1993 };
1994
1995
1996 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
1997 if (n != NULL && m != NULL) {
1998 if (m->Opcode() == Op_LoadI) {
1999 FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2000 return bmii.match(Op_AndI, -1, Op_SubI, 1, 0) ||
2001 bmii.match(Op_AndI, -1, Op_AddI, -1, -1) ||
2002 bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2003 } else if (m->Opcode() == Op_LoadL) {
2004 FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2005 return bmil.match(Op_AndL, -1, Op_SubL, 1, 0) ||
2006 bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2007 bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2008 }
2009 }
2010 return false;
2011 }
2012 #endif // X86
2013
2014 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2015 Node *off = m->in(AddPNode::Offset);
2016 if (off->is_Con()) {
2017 address_visited.test_set(m->_idx); // Flag as address_visited
2018 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2019 // Clone X+offset as it also folds into most addressing expressions
2020 mstack.push(off, Visit);
2021 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2022 return true;
2023 }
2024 return false;
2025 }
2026
2027 // A method-klass-holder may be passed in the inline_cache_reg
2028 // and then expanded into the inline_cache_reg and a method_oop register
2029 // defined in ad_<arch>.cpp
2030
2031 //------------------------------find_shared------------------------------------
2032 // Set bits if Node is shared or otherwise a root
2033 void Matcher::find_shared( Node *n ) {
2034 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2035 MStack mstack(C->live_nodes() * 2);
2036 // Mark nodes as address_visited if they are inputs to an address expression
2037 VectorSet address_visited(Thread::current()->resource_area());
2038 mstack.push(n, Visit); // Don't need to pre-visit root node
2039 while (mstack.is_nonempty()) {
2040 n = mstack.node(); // Leave node on stack
2041 Node_State nstate = mstack.state();
2042 uint nop = n->Opcode();
2043 if (nstate == Pre_Visit) {
2044 if (address_visited.test(n->_idx)) { // Visited in address already?
2045 // Flag as visited and shared now.
2046 set_visited(n);
2047 }
2048 if (is_visited(n)) { // Visited already?
2049 // Node is shared and has no reason to clone. Flag it as shared.
2050 // This causes it to match into a register for the sharing.
2051 set_shared(n); // Flag as shared and
2052 mstack.pop(); // remove node from stack
2053 continue;
2054 }
2055 nstate = Visit; // Not already visited; so visit now
2056 }
2057 if (nstate == Visit) {
2058 mstack.set_state(Post_Visit);
2059 set_visited(n); // Flag as visited now
2060 bool mem_op = false;
2061
2062 switch( nop ) { // Handle some opcodes special
2063 case Op_Phi: // Treat Phis as shared roots
2064 case Op_Parm:
2065 case Op_Proj: // All handled specially during matching
2066 case Op_SafePointScalarObject:
2067 set_shared(n);
2068 set_dontcare(n);
2069 break;
2070 case Op_If:
2071 case Op_CountedLoopEnd:
2072 mstack.set_state(Alt_Post_Visit); // Alternative way
2073 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2074 // with matching cmp/branch in 1 instruction. The Matcher needs the
2075 // Bool and CmpX side-by-side, because it can only get at constants
2076 // that are at the leaves of Match trees, and the Bool's condition acts
2077 // as a constant here.
2078 mstack.push(n->in(1), Visit); // Clone the Bool
2079 mstack.push(n->in(0), Pre_Visit); // Visit control input
2080 continue; // while (mstack.is_nonempty())
2081 case Op_ConvI2D: // These forms efficiently match with a prior
2082 case Op_ConvI2F: // Load but not a following Store
2083 if( n->in(1)->is_Load() && // Prior load
2084 n->outcnt() == 1 && // Not already shared
2085 n->unique_out()->is_Store() ) // Following store
2086 set_shared(n); // Force it to be a root
2087 break;
2088 case Op_ReverseBytesI:
2089 case Op_ReverseBytesL:
2090 if( n->in(1)->is_Load() && // Prior load
2091 n->outcnt() == 1 ) // Not already shared
2092 set_shared(n); // Force it to be a root
2093 break;
2094 case Op_BoxLock: // Cant match until we get stack-regs in ADLC
2095 case Op_IfFalse:
2096 case Op_IfTrue:
2097 case Op_MachProj:
2098 case Op_MergeMem:
2099 case Op_Catch:
2100 case Op_CatchProj:
2101 case Op_CProj:
2102 case Op_JumpProj:
2103 case Op_JProj:
2104 case Op_NeverBranch:
2105 set_dontcare(n);
2106 break;
2107 case Op_Jump:
2108 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2109 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2110 continue; // while (mstack.is_nonempty())
2111 case Op_StrComp:
2112 case Op_StrEquals:
2113 case Op_StrIndexOf:
2114 case Op_StrIndexOfChar:
2115 case Op_AryEq:
2116 case Op_HasNegatives:
2117 case Op_StrInflatedCopy:
2118 case Op_StrCompressedCopy:
2119 case Op_EncodeISOArray:
2120 set_shared(n); // Force result into register (it will be anyways)
2121 break;
2122 case Op_ConP: { // Convert pointers above the centerline to NUL
2123 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2124 const TypePtr* tp = tn->type()->is_ptr();
2125 if (tp->_ptr == TypePtr::AnyNull) {
2126 tn->set_type(TypePtr::NULL_PTR);
2127 }
2128 break;
2129 }
2130 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2131 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2132 const TypePtr* tp = tn->type()->make_ptr();
2133 if (tp && tp->_ptr == TypePtr::AnyNull) {
2134 tn->set_type(TypeNarrowOop::NULL_PTR);
2135 }
2136 break;
2137 }
2138 case Op_Binary: // These are introduced in the Post_Visit state.
2139 ShouldNotReachHere();
2140 break;
2141 case Op_ClearArray:
2142 case Op_SafePoint:
2143 mem_op = true;
2144 break;
2145 default:
2146 if( n->is_Store() ) {
2147 // Do match stores, despite no ideal reg
2148 mem_op = true;
2149 break;
2150 }
2151 if( n->is_Mem() ) { // Loads and LoadStores
2152 mem_op = true;
2153 // Loads must be root of match tree due to prior load conflict
2154 if( C->subsume_loads() == false )
2155 set_shared(n);
2156 }
2157 // Fall into default case
2158 if( !n->ideal_reg() )
2159 set_dontcare(n); // Unmatchable Nodes
2160 } // end_switch
2161
2162 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2163 Node *m = n->in(i); // Get ith input
2164 if (m == NULL) continue; // Ignore NULLs
2165 uint mop = m->Opcode();
2166
2167 // Must clone all producers of flags, or we will not match correctly.
2168 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2169 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2170 // are also there, so we may match a float-branch to int-flags and
2171 // expect the allocator to haul the flags from the int-side to the
2172 // fp-side. No can do.
2173 if( _must_clone[mop] ) {
2174 mstack.push(m, Visit);
2175 continue; // for(int i = ...)
2176 }
2177
2178 if( mop == Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2179 // Bases used in addresses must be shared but since
2180 // they are shared through a DecodeN they may appear
2181 // to have a single use so force sharing here.
2182 set_shared(m->in(AddPNode::Base)->in(1));
2183 }
2184
2185 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2186 #ifdef X86
2187 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2188 mstack.push(m, Visit);
2189 continue;
2190 }
2191 #endif
2192
2193 // Clone addressing expressions as they are "free" in memory access instructions
2194 if (mem_op && i == MemNode::Address && mop == Op_AddP &&
2195 // When there are other uses besides address expressions
2196 // put it on stack and mark as shared.
2197 !is_visited(m)) {
2198 // Some inputs for address expression are not put on stack
2199 // to avoid marking them as shared and forcing them into register
2200 // if they are used only in address expressions.
2201 // But they should be marked as shared if there are other uses
2202 // besides address expressions.
2203
2204 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2205 continue;
2206 }
2207 } // if( mem_op &&
2208 mstack.push(m, Pre_Visit);
2209 } // for(int i = ...)
2210 }
2211 else if (nstate == Alt_Post_Visit) {
2212 mstack.pop(); // Remove node from stack
2213 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2214 // shared and all users of the Bool need to move the Cmp in parallel.
2215 // This leaves both the Bool and the If pointing at the Cmp. To
2216 // prevent the Matcher from trying to Match the Cmp along both paths
2217 // BoolNode::match_edge always returns a zero.
2218
2219 // We reorder the Op_If in a pre-order manner, so we can visit without
2220 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2221 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2222 }
2223 else if (nstate == Post_Visit) {
2224 mstack.pop(); // Remove node from stack
2225
2226 // Now hack a few special opcodes
2227 switch( n->Opcode() ) { // Handle some opcodes special
2228 case Op_StorePConditional:
2229 case Op_StoreIConditional:
2230 case Op_StoreLConditional:
2231 case Op_CompareAndExchangeB:
2232 case Op_CompareAndExchangeS:
2233 case Op_CompareAndExchangeI:
2234 case Op_CompareAndExchangeL:
2235 case Op_CompareAndExchangeP:
2236 case Op_CompareAndExchangeN:
2237 case Op_WeakCompareAndSwapB:
2238 case Op_WeakCompareAndSwapS:
2239 case Op_WeakCompareAndSwapI:
2240 case Op_WeakCompareAndSwapL:
2241 case Op_WeakCompareAndSwapP:
2242 case Op_WeakCompareAndSwapN:
2243 case Op_CompareAndSwapB:
2244 case Op_CompareAndSwapS:
2245 case Op_CompareAndSwapI:
2246 case Op_CompareAndSwapL:
2247 case Op_CompareAndSwapP:
2248 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2249 Node *newval = n->in(MemNode::ValueIn );
2250 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2251 Node *pair = new BinaryNode( oldval, newval );
2252 n->set_req(MemNode::ValueIn,pair);
2253 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2254 break;
2255 }
2256 case Op_CMoveD: // Convert trinary to binary-tree
2257 case Op_CMoveF:
2258 case Op_CMoveI:
2259 case Op_CMoveL:
2260 case Op_CMoveN:
2261 case Op_CMoveP:
2262 case Op_CMoveVD: {
2263 // Restructure into a binary tree for Matching. It's possible that
2264 // we could move this code up next to the graph reshaping for IfNodes
2265 // or vice-versa, but I do not want to debug this for Ladybird.
2266 // 10/2/2000 CNC.
2267 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2268 n->set_req(1,pair1);
2269 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2270 n->set_req(2,pair2);
2271 n->del_req(3);
2272 break;
2273 }
2274 case Op_LoopLimit: {
2275 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2276 n->set_req(1,pair1);
2277 n->set_req(2,n->in(3));
2278 n->del_req(3);
2279 break;
2280 }
2281 case Op_StrEquals:
2282 case Op_StrIndexOfChar: {
2283 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2284 n->set_req(2,pair1);
2285 n->set_req(3,n->in(4));
2286 n->del_req(4);
2287 break;
2288 }
2289 case Op_StrComp:
2290 case Op_StrIndexOf: {
2291 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2292 n->set_req(2,pair1);
2293 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2294 n->set_req(3,pair2);
2295 n->del_req(5);
2296 n->del_req(4);
2297 break;
2298 }
2299 case Op_StrCompressedCopy:
2300 case Op_StrInflatedCopy:
2301 case Op_EncodeISOArray: {
2302 // Restructure into a binary tree for Matching.
2303 Node* pair = new BinaryNode(n->in(3), n->in(4));
2304 n->set_req(3, pair);
2305 n->del_req(4);
2306 break;
2307 }
2308 default:
2309 break;
2310 }
2311 }
2312 else {
2313 ShouldNotReachHere();
2314 }
2315 } // end of while (mstack.is_nonempty())
2316 }
2317
2318 #ifdef ASSERT
2319 // machine-independent root to machine-dependent root
2320 void Matcher::dump_old2new_map() {
2321 _old2new_map.dump();
2322 }
2323 #endif
2324
2325 //---------------------------collect_null_checks-------------------------------
2326 // Find null checks in the ideal graph; write a machine-specific node for
2327 // it. Used by later implicit-null-check handling. Actually collects
2328 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2329 // value being tested.
2330 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2331 Node *iff = proj->in(0);
2332 if( iff->Opcode() == Op_If ) {
2333 // During matching If's have Bool & Cmp side-by-side
2334 BoolNode *b = iff->in(1)->as_Bool();
2335 Node *cmp = iff->in(2);
2336 int opc = cmp->Opcode();
2337 if (opc != Op_CmpP && opc != Op_CmpN) return;
2338
2339 const Type* ct = cmp->in(2)->bottom_type();
2340 if (ct == TypePtr::NULL_PTR ||
2341 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2342
2343 bool push_it = false;
2344 if( proj->Opcode() == Op_IfTrue ) {
2345 #ifndef PRODUCT
2346 extern int all_null_checks_found;
2347 all_null_checks_found++;
2348 #endif
2349 if( b->_test._test == BoolTest::ne ) {
2350 push_it = true;
2351 }
2352 } else {
2353 assert( proj->Opcode() == Op_IfFalse, "" );
2354 if( b->_test._test == BoolTest::eq ) {
2355 push_it = true;
2356 }
2357 }
2358 if( push_it ) {
2359 _null_check_tests.push(proj);
2360 Node* val = cmp->in(1);
2361 #ifdef _LP64
2362 if (val->bottom_type()->isa_narrowoop() &&
2363 !Matcher::narrow_oop_use_complex_address()) {
2364 //
2365 // Look for DecodeN node which should be pinned to orig_proj.
2366 // On platforms (Sparc) which can not handle 2 adds
2367 // in addressing mode we have to keep a DecodeN node and
2368 // use it to do implicit NULL check in address.
2369 //
2370 // DecodeN node was pinned to non-null path (orig_proj) during
2371 // CastPP transformation in final_graph_reshaping_impl().
2372 //
2373 uint cnt = orig_proj->outcnt();
2414 // Is a match-tree root, so replace with the matched value
2415 _null_check_tests.map(i+1, new_val);
2416 } else {
2417 // Yank from candidate list
2418 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2419 _null_check_tests.map(i,_null_check_tests[--cnt]);
2420 _null_check_tests.pop();
2421 _null_check_tests.pop();
2422 i-=2;
2423 }
2424 }
2425 }
2426
2427 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2428 // atomic instruction acting as a store_load barrier without any
2429 // intervening volatile load, and thus we don't need a barrier here.
2430 // We retain the Node to act as a compiler ordering barrier.
2431 bool Matcher::post_store_load_barrier(const Node* vmb) {
2432 Compile* C = Compile::current();
2433 assert(vmb->is_MemBar(), "");
2434 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2435 const MemBarNode* membar = vmb->as_MemBar();
2436
2437 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2438 Node* ctrl = NULL;
2439 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2440 Node* p = membar->fast_out(i);
2441 assert(p->is_Proj(), "only projections here");
2442 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2443 !C->node_arena()->contains(p)) { // Unmatched old-space only
2444 ctrl = p;
2445 break;
2446 }
2447 }
2448 assert((ctrl != NULL), "missing control projection");
2449
2450 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2451 Node *x = ctrl->fast_out(j);
2452 int xop = x->Opcode();
2453
2454 // We don't need current barrier if we see another or a lock
2455 // before seeing volatile load.
2456 //
2457 // Op_Fastunlock previously appeared in the Op_* list below.
2458 // With the advent of 1-0 lock operations we're no longer guaranteed
2459 // that a monitor exit operation contains a serializing instruction.
2460
2461 if (xop == Op_MemBarVolatile ||
2462 xop == Op_CompareAndExchangeB ||
2463 xop == Op_CompareAndExchangeS ||
2464 xop == Op_CompareAndExchangeI ||
2465 xop == Op_CompareAndExchangeL ||
2466 xop == Op_CompareAndExchangeP ||
2467 xop == Op_CompareAndExchangeN ||
2468 xop == Op_WeakCompareAndSwapB ||
2469 xop == Op_WeakCompareAndSwapS ||
2470 xop == Op_WeakCompareAndSwapL ||
2471 xop == Op_WeakCompareAndSwapP ||
2472 xop == Op_WeakCompareAndSwapN ||
2473 xop == Op_WeakCompareAndSwapI ||
2474 xop == Op_CompareAndSwapB ||
2475 xop == Op_CompareAndSwapS ||
2476 xop == Op_CompareAndSwapL ||
2477 xop == Op_CompareAndSwapP ||
2478 xop == Op_CompareAndSwapN ||
2479 xop == Op_CompareAndSwapI) {
2480 return true;
2481 }
2482
2483 // Op_FastLock previously appeared in the Op_* list above.
2484 // With biased locking we're no longer guaranteed that a monitor
2485 // enter operation contains a serializing instruction.
2486 if ((xop == Op_FastLock) && !UseBiasedLocking) {
2487 return true;
2488 }
2489
2490 if (x->is_MemBar()) {
2491 // We must retain this membar if there is an upcoming volatile
2492 // load, which will be followed by acquire membar.
2493 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2494 return false;
2495 } else {
2496 // For other kinds of barriers, check by pretending we
2497 // are them, and seeing if we can be removed.
2498 return post_store_load_barrier(x->as_MemBar());
2499 }
2500 }
2501
2502 // probably not necessary to check for these
2503 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2504 return false;
2505 }
2506 }
2507 return false;
2508 }
2509
2510 // Check whether node n is a branch to an uncommon trap that we could
2511 // optimize as test with very high branch costs in case of going to
2512 // the uncommon trap. The code must be able to be recompiled to use
2513 // a cheaper test.
|
26 #include "memory/allocation.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "opto/ad.hpp"
29 #include "opto/addnode.hpp"
30 #include "opto/callnode.hpp"
31 #include "opto/idealGraphPrinter.hpp"
32 #include "opto/matcher.hpp"
33 #include "opto/memnode.hpp"
34 #include "opto/movenode.hpp"
35 #include "opto/opcodes.hpp"
36 #include "opto/regmask.hpp"
37 #include "opto/rootnode.hpp"
38 #include "opto/runtime.hpp"
39 #include "opto/type.hpp"
40 #include "opto/vectornode.hpp"
41 #include "runtime/os.hpp"
42 #include "runtime/sharedRuntime.hpp"
43
44 OptoReg::Name OptoReg::c_frame_pointer;
45
46 const RegMask *Matcher::idealreg2regmask[static_cast<uint>(Opcodes::_last_machine_leaf)];
47 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
48 RegMask Matcher::STACK_ONLY_mask;
49 RegMask Matcher::c_frame_ptr_mask;
50 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
51 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
52
53 //---------------------------Matcher-------------------------------------------
54 Matcher::Matcher()
55 : PhaseTransform( Phase::Ins_Select ),
56 #ifdef ASSERT
57 _old2new_map(C->comp_arena()),
58 _new2old_map(C->comp_arena()),
59 #endif
60 _shared_nodes(C->comp_arena()),
61 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
62 _swallowed(swallowed),
63 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
64 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
65 _must_clone(must_clone),
66 _register_save_policy(register_save_policy),
67 _c_reg_save_policy(c_reg_save_policy),
68 _register_save_type(register_save_type),
69 _ruleName(ruleName),
70 _allocation_started(false),
71 _states_arena(Chunk::medium_size),
72 _visited(&_states_arena),
73 _shared(&_states_arena),
74 _dontcare(&_states_arena) {
75 C->set_matcher(this);
76
77 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegI)] = NULL;
78 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegN)] = NULL;
79 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegL)] = NULL;
80 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegF)] = NULL;
81 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegD)] = NULL;
82 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegP)] = NULL;
83 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecS)] = NULL;
84 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecD)] = NULL;
85 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecX)] = NULL;
86 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecY)] = NULL;
87 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecZ)] = NULL;
88
89 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegI)] = NULL;
90 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegN)] = NULL;
91 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegL)] = NULL;
92 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegF)] = NULL;
93 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegD)] = NULL;
94 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegP)] = NULL;
95 idealreg2debugmask [static_cast<uint>(Opcodes::Op_VecS)] = NULL;
96 idealreg2debugmask [static_cast<uint>(Opcodes::Op_VecD)] = NULL;
97 idealreg2debugmask [static_cast<uint>(Opcodes::Op_VecX)] = NULL;
98 idealreg2debugmask [static_cast<uint>(Opcodes::Op_VecY)] = NULL;
99 idealreg2debugmask [static_cast<uint>(Opcodes::Op_VecZ)] = NULL;
100
101 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegI)] = NULL;
102 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegN)] = NULL;
103 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegL)] = NULL;
104 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegF)] = NULL;
105 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegD)] = NULL;
106 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegP)] = NULL;
107 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_VecS)] = NULL;
108 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_VecD)] = NULL;
109 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_VecX)] = NULL;
110 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_VecY)] = NULL;
111 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_VecZ)] = NULL;
112
113 debug_only(_mem_node = NULL;) // Ideal memory node consumed by mach node
114 }
115
116 //------------------------------warp_incoming_stk_arg------------------------
117 // This warps a VMReg into an OptoReg::Name
118 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
119 OptoReg::Name warped;
120 if( reg->is_stack() ) { // Stack slot argument?
121 warped = OptoReg::add(_old_SP, reg->reg2stack() );
122 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
123 if( warped >= _in_arg_limit )
124 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
125 if (!RegMask::can_represent_arg(warped)) {
126 // the compiler cannot represent this method's calling sequence
127 C->record_method_not_compilable("unsupported incoming calling sequence");
128 return OptoReg::Bad;
129 }
130 return warped;
131 }
168
169 //---------------------------match---------------------------------------------
170 void Matcher::match( ) {
171 if( MaxLabelRootDepth < 100 ) { // Too small?
172 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
173 MaxLabelRootDepth = 100;
174 }
175 // One-time initialization of some register masks.
176 init_spill_mask( C->root()->in(1) );
177 _return_addr_mask = return_addr();
178 #ifdef _LP64
179 // Pointers take 2 slots in 64-bit land
180 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
181 #endif
182
183 // Map a Java-signature return type into return register-value
184 // machine registers for 0, 1 and 2 returned values.
185 const TypeTuple *range = C->tf()->range();
186 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
187 // Get ideal-register return type
188 Opcodes ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
189 // Get machine return register
190 Opcodes sop = C->start()->Opcode();
191 OptoRegPair regs = return_value(ireg, false);
192
193 // And mask for same
194 _return_value_mask = RegMask(regs.first());
195 if( OptoReg::is_valid(regs.second()) )
196 _return_value_mask.Insert(regs.second());
197 }
198
199 // ---------------
200 // Frame Layout
201
202 // Need the method signature to determine the incoming argument types,
203 // because the types determine which registers the incoming arguments are
204 // in, and this affects the matched code.
205 const TypeTuple *domain = C->tf()->domain();
206 uint argcnt = domain->cnt() - TypeFunc::Parms;
207 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
208 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
209 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
210 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
402 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
403 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
404 // Do all the pre-defined register masks
405 rms[TypeFunc::Control ] = RegMask::Empty;
406 rms[TypeFunc::I_O ] = RegMask::Empty;
407 rms[TypeFunc::Memory ] = RegMask::Empty;
408 rms[TypeFunc::ReturnAdr] = ret_adr;
409 rms[TypeFunc::FramePtr ] = fp;
410 return rms;
411 }
412
413 //---------------------------init_first_stack_mask-----------------------------
414 // Create the initial stack mask used by values spilling to the stack.
415 // Disallow any debug info in outgoing argument areas by setting the
416 // initial mask accordingly.
417 void Matcher::init_first_stack_mask() {
418
419 // Allocate storage for spill masks as masks for the appropriate load type.
420 RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * (3*6+5));
421
422 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegN)] = &rms[0];
423 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegI)] = &rms[1];
424 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegL)] = &rms[2];
425 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegF)] = &rms[3];
426 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegD)] = &rms[4];
427 idealreg2spillmask [static_cast<uint>(Opcodes::Op_RegP)] = &rms[5];
428
429 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegN)] = &rms[6];
430 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegI)] = &rms[7];
431 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegL)] = &rms[8];
432 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegF)] = &rms[9];
433 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegD)] = &rms[10];
434 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegP)] = &rms[11];
435
436 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegN)] = &rms[12];
437 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegI)] = &rms[13];
438 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegL)] = &rms[14];
439 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegF)] = &rms[15];
440 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegD)] = &rms[16];
441 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegP)] = &rms[17];
442
443 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecS)] = &rms[18];
444 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecD)] = &rms[19];
445 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecX)] = &rms[20];
446 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecY)] = &rms[21];
447 idealreg2spillmask [static_cast<uint>(Opcodes::Op_VecZ)] = &rms[22];
448
449 OptoReg::Name i;
450
451 // At first, start with the empty mask
452 C->FIRST_STACK_mask().Clear();
453
454 // Add in the incoming argument area
455 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
456 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
457 C->FIRST_STACK_mask().Insert(i);
458 }
459 // Add in all bits past the outgoing argument area
460 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
461 "must be able to represent all call arguments in reg mask");
462 OptoReg::Name init = _out_arg_limit;
463 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
464 C->FIRST_STACK_mask().Insert(i);
465 }
466 // Finally, set the "infinite stack" bit.
467 C->FIRST_STACK_mask().set_AllStack();
468
469 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
470 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
471 // Keep spill masks aligned.
472 aligned_stack_mask.clear_to_pairs();
473 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
474
475 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegP)];
476 #ifdef _LP64
477 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegN)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegN)];
478 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegN)]->OR(C->FIRST_STACK_mask());
479 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)]->OR(aligned_stack_mask);
480 #else
481 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)]->OR(C->FIRST_STACK_mask());
482 #endif
483 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegI)];
484 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)]->OR(C->FIRST_STACK_mask());
485 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegL)];
486 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)]->OR(aligned_stack_mask);
487 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegF)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegF)];
488 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegF)]->OR(C->FIRST_STACK_mask());
489 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_RegD)];
490 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)]->OR(aligned_stack_mask);
491
492 if (Matcher::vector_size_supported(T_BYTE,4)) {
493 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecS)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_VecS)];
494 idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecS)]->OR(C->FIRST_STACK_mask());
495 }
496 if (Matcher::vector_size_supported(T_FLOAT,2)) {
497 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
498 // RA guarantees such alignment since it is needed for Double and Long values.
499 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecD)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_VecD)];
500 idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecD)]->OR(aligned_stack_mask);
501 }
502 if (Matcher::vector_size_supported(T_FLOAT,4)) {
503 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
504 //
505 // RA can use input arguments stack slots for spills but until RA
506 // we don't know frame size and offset of input arg stack slots.
507 //
508 // Exclude last input arg stack slots to avoid spilling vectors there
509 // otherwise vector spills could stomp over stack slots in caller frame.
510 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
511 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
512 aligned_stack_mask.Remove(in);
513 in = OptoReg::add(in, -1);
514 }
515 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
516 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
517 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecX)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_VecX)];
518 idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecX)]->OR(aligned_stack_mask);
519 }
520 if (Matcher::vector_size_supported(T_FLOAT,8)) {
521 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
522 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
523 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
524 aligned_stack_mask.Remove(in);
525 in = OptoReg::add(in, -1);
526 }
527 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
528 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
529 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecY)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_VecY)];
530 idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecY)]->OR(aligned_stack_mask);
531 }
532 if (Matcher::vector_size_supported(T_FLOAT,16)) {
533 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
534 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
535 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
536 aligned_stack_mask.Remove(in);
537 in = OptoReg::add(in, -1);
538 }
539 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
540 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
541 *idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecZ)] = *idealreg2regmask[static_cast<uint>(Opcodes::Op_VecZ)];
542 idealreg2spillmask[static_cast<uint>(Opcodes::Op_VecZ)]->OR(aligned_stack_mask);
543 }
544 if (UseFPUForSpilling) {
545 // This mask logic assumes that the spill operations are
546 // symmetric and that the registers involved are the same size.
547 // On sparc for instance we may have to use 64 bit moves will
548 // kill 2 registers when used with F0-F31.
549 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegF)]);
550 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegF)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegI)]);
551 #ifdef _LP64
552 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegN)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegF)]);
553 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegD)]);
554 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegL)]);
555 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegD)]);
556 #else
557 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegF)]);
558 #ifdef ARM
559 // ARM has support for moving 64bit values between a pair of
560 // integer registers and a double register
561 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegD)]);
562 idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)]->OR(*idealreg2regmask[static_cast<uint>(Opcodes::Op_RegL)]);
563 #endif
564 #endif
565 }
566
567 // Make up debug masks. Any spill slot plus callee-save registers.
568 // Caller-save registers are assumed to be trashable by the various
569 // inline-cache fixup routines.
570 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegN)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegN)];
571 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegI)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)];
572 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegL)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)];
573 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegF)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegF)];
574 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegD)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)];
575 *idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegP)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)];
576
577 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegN)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegN)];
578 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegI)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegI)];
579 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegL)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegL)];
580 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegF)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegF)];
581 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegD)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegD)];
582 *idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegP)]= *idealreg2spillmask[static_cast<uint>(Opcodes::Op_RegP)];
583
584 // Prevent stub compilations from attempting to reference
585 // callee-saved registers from debug info
586 bool exclude_soe = !Compile::current()->is_method_compilation();
587
588 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
589 // registers the caller has to save do not work
590 if( _register_save_policy[i] == 'C' ||
591 _register_save_policy[i] == 'A' ||
592 (_register_save_policy[i] == 'E' && exclude_soe) ) {
593 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegN)]->Remove(i);
594 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegI)]->Remove(i); // Exclude save-on-call
595 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegL)]->Remove(i); // registers from debug
596 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegF)]->Remove(i); // masks
597 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegD)]->Remove(i);
598 idealreg2debugmask [static_cast<uint>(Opcodes::Op_RegP)]->Remove(i);
599
600 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegN)]->Remove(i);
601 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegI)]->Remove(i);
602 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegL)]->Remove(i);
603 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegF)]->Remove(i);
604 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegD)]->Remove(i);
605 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegP)]->Remove(i);
606 }
607 }
608
609 // Subtract the register we use to save the SP for MethodHandle
610 // invokes to from the debug mask.
611 const RegMask save_mask = method_handle_invoke_SP_save_mask();
612 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegN)]->SUBTRACT(save_mask);
613 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegI)]->SUBTRACT(save_mask);
614 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegL)]->SUBTRACT(save_mask);
615 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegF)]->SUBTRACT(save_mask);
616 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegD)]->SUBTRACT(save_mask);
617 idealreg2mhdebugmask[static_cast<uint>(Opcodes::Op_RegP)]->SUBTRACT(save_mask);
618 }
619
620 //---------------------------is_save_on_entry----------------------------------
621 bool Matcher::is_save_on_entry( int reg ) {
622 return
623 _register_save_policy[reg] == 'E' ||
624 _register_save_policy[reg] == 'A' || // Save-on-entry register?
625 // Also save argument registers in the trampolining stubs
626 (C->save_argument_registers() && is_spillable_arg(reg));
627 }
628
629 //---------------------------Fixup_Save_On_Entry-------------------------------
630 void Matcher::Fixup_Save_On_Entry( ) {
631 init_first_stack_mask();
632
633 Node *root = C->root(); // Short name for root
634 // Count number of save-on-entry registers.
635 uint soe_cnt = number_of_saved_registers();
636 uint i;
637
665 #ifdef _LP64
666 // Need two slots for ptrs in 64-bit land
667 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
668 #endif
669 }
670
671 // Input RegMask array shared by all TailCalls
672 uint tail_call_edge_cnt = TypeFunc::Parms+2;
673 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
674
675 // Input RegMask array shared by all TailJumps
676 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
677 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
678
679 // TailCalls have 2 returned values (target & moop), whose masks come
680 // from the usual MachNode/MachOper mechanism. Find a sample
681 // TailCall to extract these masks and put the correct masks into
682 // the tail_call_rms array.
683 for( i=1; i < root->req(); i++ ) {
684 MachReturnNode *m = root->in(i)->as_MachReturn();
685 if( m->ideal_Opcode() == Opcodes::Op_TailCall ) {
686 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
687 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
688 break;
689 }
690 }
691
692 // TailJumps have 2 returned values (target & ex_oop), whose masks come
693 // from the usual MachNode/MachOper mechanism. Find a sample
694 // TailJump to extract these masks and put the correct masks into
695 // the tail_jump_rms array.
696 for( i=1; i < root->req(); i++ ) {
697 MachReturnNode *m = root->in(i)->as_MachReturn();
698 if( m->ideal_Opcode() == Opcodes::Op_TailJump ) {
699 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
700 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
701 break;
702 }
703 }
704
705 // Input RegMask array shared by all Halts
706 uint halt_edge_cnt = TypeFunc::Parms;
707 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
708
709 // Capture the return input masks into each exit flavor
710 for( i=1; i < root->req(); i++ ) {
711 MachReturnNode *exit = root->in(i)->as_MachReturn();
712 switch( exit->ideal_Opcode() ) {
713 case Opcodes::Op_Return : exit->_in_rms = ret_rms; break;
714 case Opcodes::Op_Rethrow : exit->_in_rms = reth_rms; break;
715 case Opcodes::Op_TailCall : exit->_in_rms = tail_call_rms; break;
716 case Opcodes::Op_TailJump : exit->_in_rms = tail_jump_rms; break;
717 case Opcodes::Op_Halt : exit->_in_rms = halt_rms; break;
718 default : ShouldNotReachHere();
719 }
720 }
721
722 // Next unused projection number from Start.
723 int proj_cnt = C->tf()->domain()->cnt();
724
725 // Do all the save-on-entry registers. Make projections from Start for
726 // them, and give them a use at the exit points. To the allocator, they
727 // look like incoming register arguments.
728 for( i = 0; i < _last_Mach_Reg; i++ ) {
729 if( is_save_on_entry(i) ) {
730
731 // Add the save-on-entry to the mask array
732 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
733 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
734 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
735 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
736 // Halts need the SOE registers, but only in the stack as debug info.
737 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
738 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[static_cast<uint>(_register_save_type[i])];
739
740 Node *mproj;
741
742 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
743 // into a single RegD.
744 if( (i&1) == 0 &&
745 _register_save_type[i ] == Opcodes::Op_RegF &&
746 _register_save_type[i+1] == Opcodes::Op_RegF &&
747 is_save_on_entry(i+1) ) {
748 // Add other bit for double
749 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
750 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
751 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
752 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
753 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
754 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Opcodes::Op_RegD );
755 proj_cnt += 2; // Skip 2 for doubles
756 }
757 else if( (i&1) == 1 && // Else check for high half of double
758 _register_save_type[i-1] == Opcodes::Op_RegF &&
759 _register_save_type[i ] == Opcodes::Op_RegF &&
760 is_save_on_entry(i-1) ) {
761 ret_rms [ ret_edge_cnt] = RegMask::Empty;
762 reth_rms [ reth_edge_cnt] = RegMask::Empty;
763 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
764 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
765 halt_rms [ halt_edge_cnt] = RegMask::Empty;
766 mproj = C->top();
767 }
768 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
769 // into a single RegL.
770 else if( (i&1) == 0 &&
771 _register_save_type[i ] == Opcodes::Op_RegI &&
772 _register_save_type[i+1] == Opcodes::Op_RegI &&
773 is_save_on_entry(i+1) ) {
774 // Add other bit for long
775 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
776 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
777 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
778 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
779 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
780 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Opcodes::Op_RegL );
781 proj_cnt += 2; // Skip 2 for longs
782 }
783 else if( (i&1) == 1 && // Else check for high half of long
784 _register_save_type[i-1] == Opcodes::Op_RegI &&
785 _register_save_type[i ] == Opcodes::Op_RegI &&
786 is_save_on_entry(i-1) ) {
787 ret_rms [ ret_edge_cnt] = RegMask::Empty;
788 reth_rms [ reth_edge_cnt] = RegMask::Empty;
789 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
790 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
791 halt_rms [ halt_edge_cnt] = RegMask::Empty;
792 mproj = C->top();
793 } else {
794 // Make a projection for it off the Start
795 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
796 }
797
798 ret_edge_cnt ++;
799 reth_edge_cnt ++;
800 tail_call_edge_cnt ++;
801 tail_jump_edge_cnt ++;
802 halt_edge_cnt ++;
803
804 // Add a use of the SOE register to all exit paths
805 for( uint j=1; j < root->req(); j++ )
806 root->in(j)->add_req(mproj);
807 } // End of if a save-on-entry register
808 } // End of for all machine registers
809 }
810
811 //------------------------------init_spill_mask--------------------------------
812 void Matcher::init_spill_mask( Node *ret ) {
813 if( idealreg2regmask[static_cast<uint>(Opcodes::Op_RegI)] ) return; // One time only init
814
815 OptoReg::c_frame_pointer = c_frame_pointer();
816 c_frame_ptr_mask = c_frame_pointer();
817 #ifdef _LP64
818 // pointers are twice as big
819 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
820 #endif
821
822 // Start at OptoReg::stack0()
823 STACK_ONLY_mask.Clear();
824 OptoReg::Name init = OptoReg::stack2reg(0);
825 // STACK_ONLY_mask is all stack bits
826 OptoReg::Name i;
827 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
828 STACK_ONLY_mask.Insert(i);
829 // Also set the "infinite stack" bit.
830 STACK_ONLY_mask.set_AllStack();
831
832 // Copy the register names over into the shared world
833 for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
839 // Grab the Frame Pointer
840 Node *fp = ret->in(TypeFunc::FramePtr);
841 Node *mem = ret->in(TypeFunc::Memory);
842 const TypePtr* atp = TypePtr::BOTTOM;
843 // Share frame pointer while making spill ops
844 set_shared(fp);
845
846 // Compute generic short-offset Loads
847 #ifdef _LP64
848 MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
849 #endif
850 MachNode *spillI = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
851 MachNode *spillL = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
852 MachNode *spillF = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
853 MachNode *spillD = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
854 MachNode *spillP = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
855 assert(spillI != NULL && spillL != NULL && spillF != NULL &&
856 spillD != NULL && spillP != NULL, "");
857 // Get the ADLC notion of the right regmask, for each basic type.
858 #ifdef _LP64
859 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegN)] = &spillCP->out_RegMask();
860 #endif
861 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegI)] = &spillI->out_RegMask();
862 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegL)] = &spillL->out_RegMask();
863 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegF)] = &spillF->out_RegMask();
864 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegD)] = &spillD->out_RegMask();
865 idealreg2regmask[static_cast<uint>(Opcodes::Op_RegP)] = &spillP->out_RegMask();
866
867 // Vector regmasks.
868 if (Matcher::vector_size_supported(T_BYTE,4)) {
869 TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
870 MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
871 idealreg2regmask[static_cast<uint>(Opcodes::Op_VecS)] = &spillVectS->out_RegMask();
872 }
873 if (Matcher::vector_size_supported(T_FLOAT,2)) {
874 MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
875 idealreg2regmask[static_cast<uint>(Opcodes::Op_VecD)] = &spillVectD->out_RegMask();
876 }
877 if (Matcher::vector_size_supported(T_FLOAT,4)) {
878 MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
879 idealreg2regmask[static_cast<uint>(Opcodes::Op_VecX)] = &spillVectX->out_RegMask();
880 }
881 if (Matcher::vector_size_supported(T_FLOAT,8)) {
882 MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
883 idealreg2regmask[static_cast<uint>(Opcodes::Op_VecY)] = &spillVectY->out_RegMask();
884 }
885 if (Matcher::vector_size_supported(T_FLOAT,16)) {
886 MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
887 idealreg2regmask[static_cast<uint>(Opcodes::Op_VecZ)] = &spillVectZ->out_RegMask();
888 }
889 }
890
891 #ifdef ASSERT
892 static void match_alias_type(Compile* C, Node* n, Node* m) {
893 if (!VerifyAliases) return; // do not go looking for trouble by default
894 const TypePtr* nat = n->adr_type();
895 const TypePtr* mat = m->adr_type();
896 int nidx = C->get_alias_index(nat);
897 int midx = C->get_alias_index(mat);
898 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
899 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
900 for (uint i = 1; i < n->req(); i++) {
901 Node* n1 = n->in(i);
902 const TypePtr* n1at = n1->adr_type();
903 if (n1at != NULL) {
904 nat = n1at;
905 nidx = C->get_alias_index(n1at);
906 }
907 }
908 }
909 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
910 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
911 switch (n->Opcode()) {
912 case Opcodes::Op_PrefetchAllocation:
913 nidx = Compile::AliasIdxRaw;
914 nat = TypeRawPtr::BOTTOM;
915 break;
916 }
917 }
918 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
919 switch (n->Opcode()) {
920 case Opcodes::Op_ClearArray:
921 midx = Compile::AliasIdxRaw;
922 mat = TypeRawPtr::BOTTOM;
923 break;
924 }
925 }
926 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
927 switch (n->Opcode()) {
928 case Opcodes::Op_Return:
929 case Opcodes::Op_Rethrow:
930 case Opcodes::Op_Halt:
931 case Opcodes::Op_TailCall:
932 case Opcodes::Op_TailJump:
933 nidx = Compile::AliasIdxBot;
934 nat = TypePtr::BOTTOM;
935 break;
936 }
937 }
938 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
939 switch (n->Opcode()) {
940 case Opcodes::Op_StrComp:
941 case Opcodes::Op_StrEquals:
942 case Opcodes::Op_StrIndexOf:
943 case Opcodes::Op_StrIndexOfChar:
944 case Opcodes::Op_AryEq:
945 case Opcodes::Op_HasNegatives:
946 case Opcodes::Op_MemBarVolatile:
947 case Opcodes::Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
948 case Opcodes::Op_StrInflatedCopy:
949 case Opcodes::Op_StrCompressedCopy:
950 case Opcodes::Op_OnSpinWait:
951 case Opcodes::Op_EncodeISOArray:
952 nidx = Compile::AliasIdxTop;
953 nat = NULL;
954 break;
955 }
956 }
957 if (nidx != midx) {
958 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
959 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
960 n->dump();
961 m->dump();
962 }
963 assert(C->subsume_loads() && C->must_alias(nat, midx),
964 "must not lose alias info when matching");
965 }
966 }
967 #endif
968
969 //------------------------------xform------------------------------------------
970 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
971 // Node in new-space. Given a new-space Node, recursively walk his children.
1043 // Handle precedence edges for interior nodes
1044 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1045 Node *m = n->in(i);
1046 if (m == NULL || C->node_arena()->contains(m)) continue;
1047 n->rm_prec(i);
1048 // set -1 to call add_prec() instead of set_req() during Step1
1049 mstack.push(m, Visit, n, -1);
1050 }
1051
1052 // For constant debug info, I'd rather have unmatched constants.
1053 int cnt = n->req();
1054 JVMState* jvms = n->jvms();
1055 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1056
1057 // Now do only debug info. Clone constants rather than matching.
1058 // Constants are represented directly in the debug info without
1059 // the need for executable machine instructions.
1060 // Monitor boxes are also represented directly.
1061 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1062 Node *m = n->in(i); // Get input
1063 Opcodes op = m->Opcode();
1064 assert((op == Opcodes::Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1065 if( op == Opcodes::Op_ConI || op == Opcodes::Op_ConP || op == Opcodes::Op_ConN || op == Opcodes::Op_ConNKlass ||
1066 op == Opcodes::Op_ConF || op == Opcodes::Op_ConD || op == Opcodes::Op_ConL
1067 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1068 ) {
1069 m = m->clone();
1070 #ifdef ASSERT
1071 _new2old_map.map(m->_idx, n);
1072 #endif
1073 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1074 mstack.push(m->in(0), Visit, m, 0);
1075 } else {
1076 mstack.push(m, Visit, n, i);
1077 }
1078 }
1079
1080 // And now walk his children, and convert his inputs to new-space.
1081 for( ; i >= 0; --i ) { // For all normal inputs do
1082 Node *m = n->in(i); // Get input
1083 if(m != NULL)
1084 mstack.push(m, Visit, n, i);
1085 }
1086
1281 } // End of for all arguments
1282
1283 // Compute number of stack slots needed to restore stack in case of
1284 // Pascal-style argument popping.
1285 mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1286 }
1287
1288 // Compute the max stack slot killed by any call. These will not be
1289 // available for debug info, and will be used to adjust FIRST_STACK_mask
1290 // after all call sites have been visited.
1291 if( _out_arg_limit < out_arg_limit_per_call)
1292 _out_arg_limit = out_arg_limit_per_call;
1293
1294 if (mcall) {
1295 // Kill the outgoing argument area, including any non-argument holes and
1296 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1297 // Since the max-per-method covers the max-per-call-site and debug info
1298 // is excluded on the max-per-method basis, debug info cannot land in
1299 // this killed area.
1300 uint r_cnt = mcall->tf()->range()->cnt();
1301 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, static_cast<Opcodes>(MachProjNode::projType::fat_proj) );
1302 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1303 C->record_method_not_compilable("unsupported outgoing calling sequence");
1304 } else {
1305 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1306 proj->_rout.Insert(OptoReg::Name(i));
1307 }
1308 if (proj->_rout.is_NotEmpty()) {
1309 push_projection(proj);
1310 }
1311 }
1312 // Transfer the safepoint information from the call to the mcall
1313 // Move the JVMState list
1314 msfpt->set_jvms(sfpt->jvms());
1315 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1316 jvms->set_map(sfpt);
1317 }
1318
1319 // Debug inputs begin just after the last incoming parameter
1320 assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1321 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1329 // ins are not complete then.
1330 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1331 if (msfpt->jvms() &&
1332 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1333 // We added an edge before jvms, so we must adapt the position of the ins.
1334 msfpt->jvms()->adapt_position(+1);
1335 }
1336 }
1337
1338 // Registers killed by the call are set in the local scheduling pass
1339 // of Global Code Motion.
1340 return msfpt;
1341 }
1342
1343 //---------------------------match_tree----------------------------------------
1344 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1345 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1346 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1347 // a Load's result RegMask for memoization in idealreg2regmask[]
1348 MachNode *Matcher::match_tree( const Node *n ) {
1349 assert( n->Opcode() != Opcodes::Op_Phi, "cannot match" );
1350 assert( !n->is_block_start(), "cannot match" );
1351 // Set the mark for all locally allocated State objects.
1352 // When this call returns, the _states_arena arena will be reset
1353 // freeing all State objects.
1354 ResourceMark rm( &_states_arena );
1355
1356 LabelRootDepth = 0;
1357
1358 // StoreNodes require their Memory input to match any LoadNodes
1359 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1360 #ifdef ASSERT
1361 Node* save_mem_node = _mem_node;
1362 _mem_node = n->is_Store() ? (Node*)n : NULL;
1363 #endif
1364 // State object for root node of match tree
1365 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1366 State *s = new (&_states_arena) State;
1367 s->_kids[0] = NULL;
1368 s->_kids[1] = NULL;
1369 s->_leaf = (Node*)n;
1908 BasicType sig_bt = T_OBJECT;
1909 calling_convention(&sig_bt, ®s, 1, is_outgoing);
1910 // Return argument 0 register. In the LP64 build pointers
1911 // take 2 registers, but the VM wants only the 'main' name.
1912 return OptoReg::as_OptoReg(regs.first());
1913 }
1914
1915 // This function identifies sub-graphs in which a 'load' node is
1916 // input to two different nodes, and such that it can be matched
1917 // with BMI instructions like blsi, blsr, etc.
1918 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1919 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1920 // refers to the same node.
1921 #ifdef X86
1922 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
1923 // This is a temporary solution until we make DAGs expressible in ADL.
1924 template<typename ConType>
1925 class FusedPatternMatcher {
1926 Node* _op1_node;
1927 Node* _mop_node;
1928 Opcodes _con_op;
1929
1930 static int match_next(Node* n, Opcodes next_op, int next_op_idx) {
1931 if (n->in(1) == NULL || n->in(2) == NULL) {
1932 return -1;
1933 }
1934
1935 if (next_op_idx == -1) { // n is commutative, try rotations
1936 if (n->in(1)->Opcode() == next_op) {
1937 return 1;
1938 } else if (n->in(2)->Opcode() == next_op) {
1939 return 2;
1940 }
1941 } else {
1942 assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
1943 if (n->in(next_op_idx)->Opcode() == next_op) {
1944 return next_op_idx;
1945 }
1946 }
1947 return -1;
1948 }
1949 public:
1950 FusedPatternMatcher(Node* op1_node, Node *mop_node, Opcodes con_op) :
1951 _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
1952
1953 bool match(Opcodes op1, int op1_op2_idx, // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
1954 Opcodes op2, int op2_con_idx, // op2 and the index of the op2->con edge, -1 if op2 is commutative
1955 typename ConType::NativeType con_value) {
1956 if (_op1_node->Opcode() != op1) {
1957 return false;
1958 }
1959 if (_mop_node->outcnt() > 2) {
1960 return false;
1961 }
1962 op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
1963 if (op1_op2_idx == -1) {
1964 return false;
1965 }
1966 // Memory operation must be the other edge
1967 int op1_mop_idx = (op1_op2_idx & 1) + 1;
1968
1969 // Check that the mop node is really what we want
1970 if (_op1_node->in(op1_mop_idx) == _mop_node) {
1971 Node *op2_node = _op1_node->in(op1_op2_idx);
1972 if (op2_node->outcnt() > 1) {
1973 return false;
1974 }
1978 return false;
1979 }
1980 // Memory operation must be the other edge
1981 int op2_mop_idx = (op2_con_idx & 1) + 1;
1982 // Check that the memory operation is the same node
1983 if (op2_node->in(op2_mop_idx) == _mop_node) {
1984 // Now check the constant
1985 const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
1986 if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
1987 return true;
1988 }
1989 }
1990 }
1991 return false;
1992 }
1993 };
1994
1995
1996 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
1997 if (n != NULL && m != NULL) {
1998 if (m->Opcode() == Opcodes::Op_LoadI) {
1999 FusedPatternMatcher<TypeInt> bmii(n, m, Opcodes::Op_ConI);
2000 return bmii.match(Opcodes::Op_AndI, -1, Opcodes::Op_SubI, 1, 0) ||
2001 bmii.match(Opcodes::Op_AndI, -1, Opcodes::Op_AddI, -1, -1) ||
2002 bmii.match(Opcodes::Op_XorI, -1, Opcodes::Op_AddI, -1, -1);
2003 } else if (m->Opcode() == Opcodes::Op_LoadL) {
2004 FusedPatternMatcher<TypeLong> bmil(n, m, Opcodes::Op_ConL);
2005 return bmil.match(Opcodes::Op_AndL, -1, Opcodes::Op_SubL, 1, 0) ||
2006 bmil.match(Opcodes::Op_AndL, -1, Opcodes::Op_AddL, -1, -1) ||
2007 bmil.match(Opcodes::Op_XorL, -1, Opcodes::Op_AddL, -1, -1);
2008 }
2009 }
2010 return false;
2011 }
2012 #endif // X86
2013
2014 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2015 Node *off = m->in(AddPNode::Offset);
2016 if (off->is_Con()) {
2017 address_visited.test_set(m->_idx); // Flag as address_visited
2018 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2019 // Clone X+offset as it also folds into most addressing expressions
2020 mstack.push(off, Visit);
2021 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2022 return true;
2023 }
2024 return false;
2025 }
2026
2027 // A method-klass-holder may be passed in the inline_cache_reg
2028 // and then expanded into the inline_cache_reg and a method_oop register
2029 // defined in ad_<arch>.cpp
2030
2031 //------------------------------find_shared------------------------------------
2032 // Set bits if Node is shared or otherwise a root
2033 void Matcher::find_shared( Node *n ) {
2034 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2035 MStack mstack(C->live_nodes() * 2);
2036 // Mark nodes as address_visited if they are inputs to an address expression
2037 VectorSet address_visited(Thread::current()->resource_area());
2038 mstack.push(n, Visit); // Don't need to pre-visit root node
2039 while (mstack.is_nonempty()) {
2040 n = mstack.node(); // Leave node on stack
2041 Node_State nstate = mstack.state();
2042 Opcodes nop = n->Opcode();
2043 if (nstate == Pre_Visit) {
2044 if (address_visited.test(n->_idx)) { // Visited in address already?
2045 // Flag as visited and shared now.
2046 set_visited(n);
2047 }
2048 if (is_visited(n)) { // Visited already?
2049 // Node is shared and has no reason to clone. Flag it as shared.
2050 // This causes it to match into a register for the sharing.
2051 set_shared(n); // Flag as shared and
2052 mstack.pop(); // remove node from stack
2053 continue;
2054 }
2055 nstate = Visit; // Not already visited; so visit now
2056 }
2057 if (nstate == Visit) {
2058 mstack.set_state(Post_Visit);
2059 set_visited(n); // Flag as visited now
2060 bool mem_op = false;
2061
2062 switch( nop ) { // Handle some opcodes special
2063 case Opcodes::Op_Phi: // Treat Phis as shared roots
2064 case Opcodes::Op_Parm:
2065 case Opcodes::Op_Proj: // All handled specially during matching
2066 case Opcodes::Op_SafePointScalarObject:
2067 set_shared(n);
2068 set_dontcare(n);
2069 break;
2070 case Opcodes::Op_If:
2071 case Opcodes::Op_CountedLoopEnd:
2072 mstack.set_state(Alt_Post_Visit); // Alternative way
2073 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2074 // with matching cmp/branch in 1 instruction. The Matcher needs the
2075 // Bool and CmpX side-by-side, because it can only get at constants
2076 // that are at the leaves of Match trees, and the Bool's condition acts
2077 // as a constant here.
2078 mstack.push(n->in(1), Visit); // Clone the Bool
2079 mstack.push(n->in(0), Pre_Visit); // Visit control input
2080 continue; // while (mstack.is_nonempty())
2081 case Opcodes::Op_ConvI2D: // These forms efficiently match with a prior
2082 case Opcodes::Op_ConvI2F: // Load but not a following Store
2083 if( n->in(1)->is_Load() && // Prior load
2084 n->outcnt() == 1 && // Not already shared
2085 n->unique_out()->is_Store() ) // Following store
2086 set_shared(n); // Force it to be a root
2087 break;
2088 case Opcodes::Op_ReverseBytesI:
2089 case Opcodes::Op_ReverseBytesL:
2090 if( n->in(1)->is_Load() && // Prior load
2091 n->outcnt() == 1 ) // Not already shared
2092 set_shared(n); // Force it to be a root
2093 break;
2094 case Opcodes::Op_BoxLock: // Cant match until we get stack-regs in ADLC
2095 case Opcodes::Op_IfFalse:
2096 case Opcodes::Op_IfTrue:
2097 case Opcodes::Op_MachProj:
2098 case Opcodes::Op_MergeMem:
2099 case Opcodes::Op_Catch:
2100 case Opcodes::Op_CatchProj:
2101 case Opcodes::Op_CProj:
2102 case Opcodes::Op_JumpProj:
2103 case Opcodes::Op_JProj:
2104 case Opcodes::Op_NeverBranch:
2105 set_dontcare(n);
2106 break;
2107 case Opcodes::Op_Jump:
2108 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2109 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2110 continue; // while (mstack.is_nonempty())
2111 case Opcodes::Op_StrComp:
2112 case Opcodes::Op_StrEquals:
2113 case Opcodes::Op_StrIndexOf:
2114 case Opcodes::Op_StrIndexOfChar:
2115 case Opcodes::Op_AryEq:
2116 case Opcodes::Op_HasNegatives:
2117 case Opcodes::Op_StrInflatedCopy:
2118 case Opcodes::Op_StrCompressedCopy:
2119 case Opcodes::Op_EncodeISOArray:
2120 set_shared(n); // Force result into register (it will be anyways)
2121 break;
2122 case Opcodes::Op_ConP: { // Convert pointers above the centerline to NUL
2123 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2124 const TypePtr* tp = tn->type()->is_ptr();
2125 if (tp->_ptr == TypePtr::AnyNull) {
2126 tn->set_type(TypePtr::NULL_PTR);
2127 }
2128 break;
2129 }
2130 case Opcodes::Op_ConN: { // Convert narrow pointers above the centerline to NUL
2131 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2132 const TypePtr* tp = tn->type()->make_ptr();
2133 if (tp && tp->_ptr == TypePtr::AnyNull) {
2134 tn->set_type(TypeNarrowOop::NULL_PTR);
2135 }
2136 break;
2137 }
2138 case Opcodes::Op_Binary: // These are introduced in the Post_Visit state.
2139 ShouldNotReachHere();
2140 break;
2141 case Opcodes::Op_ClearArray:
2142 case Opcodes::Op_SafePoint:
2143 mem_op = true;
2144 break;
2145 default:
2146 if( n->is_Store() ) {
2147 // Do match stores, despite no ideal reg
2148 mem_op = true;
2149 break;
2150 }
2151 if( n->is_Mem() ) { // Loads and LoadStores
2152 mem_op = true;
2153 // Loads must be root of match tree due to prior load conflict
2154 if( C->subsume_loads() == false )
2155 set_shared(n);
2156 }
2157 // Fall into default case
2158 if( n->ideal_reg() != Opcodes::Op_Node )
2159 set_dontcare(n); // Unmatchable Nodes
2160 } // end_switch
2161
2162 for(int i = n->req() - 1; i >= 0; --i) { // For my children
2163 Node *m = n->in(i); // Get ith input
2164 if (m == NULL) continue; // Ignore NULLs
2165 Opcodes mop = m->Opcode();
2166
2167 // Must clone all producers of flags, or we will not match correctly.
2168 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2169 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2170 // are also there, so we may match a float-branch to int-flags and
2171 // expect the allocator to haul the flags from the int-side to the
2172 // fp-side. No can do.
2173 if( _must_clone[static_cast<uint>(mop)] ) {
2174 mstack.push(m, Visit);
2175 continue; // for(int i = ...)
2176 }
2177
2178 if( mop == Opcodes::Op_AddP && m->in(AddPNode::Base)->is_DecodeNarrowPtr()) {
2179 // Bases used in addresses must be shared but since
2180 // they are shared through a DecodeN they may appear
2181 // to have a single use so force sharing here.
2182 set_shared(m->in(AddPNode::Base)->in(1));
2183 }
2184
2185 // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2186 #ifdef X86
2187 if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2188 mstack.push(m, Visit);
2189 continue;
2190 }
2191 #endif
2192
2193 // Clone addressing expressions as they are "free" in memory access instructions
2194 if (mem_op && i == MemNode::Address && mop == Opcodes::Op_AddP &&
2195 // When there are other uses besides address expressions
2196 // put it on stack and mark as shared.
2197 !is_visited(m)) {
2198 // Some inputs for address expression are not put on stack
2199 // to avoid marking them as shared and forcing them into register
2200 // if they are used only in address expressions.
2201 // But they should be marked as shared if there are other uses
2202 // besides address expressions.
2203
2204 if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2205 continue;
2206 }
2207 } // if( mem_op &&
2208 mstack.push(m, Pre_Visit);
2209 } // for(int i = ...)
2210 }
2211 else if (nstate == Alt_Post_Visit) {
2212 mstack.pop(); // Remove node from stack
2213 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2214 // shared and all users of the Bool need to move the Cmp in parallel.
2215 // This leaves both the Bool and the If pointing at the Cmp. To
2216 // prevent the Matcher from trying to Match the Cmp along both paths
2217 // BoolNode::match_edge always returns a zero.
2218
2219 // We reorder the Op_If in a pre-order manner, so we can visit without
2220 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2221 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2222 }
2223 else if (nstate == Post_Visit) {
2224 mstack.pop(); // Remove node from stack
2225
2226 // Now hack a few special opcodes
2227 switch( n->Opcode() ) { // Handle some opcodes special
2228 case Opcodes::Op_StorePConditional:
2229 case Opcodes::Op_StoreIConditional:
2230 case Opcodes::Op_StoreLConditional:
2231 case Opcodes::Op_CompareAndExchangeB:
2232 case Opcodes::Op_CompareAndExchangeS:
2233 case Opcodes::Op_CompareAndExchangeI:
2234 case Opcodes::Op_CompareAndExchangeL:
2235 case Opcodes::Op_CompareAndExchangeP:
2236 case Opcodes::Op_CompareAndExchangeN:
2237 case Opcodes::Op_WeakCompareAndSwapB:
2238 case Opcodes::Op_WeakCompareAndSwapS:
2239 case Opcodes::Op_WeakCompareAndSwapI:
2240 case Opcodes::Op_WeakCompareAndSwapL:
2241 case Opcodes::Op_WeakCompareAndSwapP:
2242 case Opcodes::Op_WeakCompareAndSwapN:
2243 case Opcodes::Op_CompareAndSwapB:
2244 case Opcodes::Op_CompareAndSwapS:
2245 case Opcodes::Op_CompareAndSwapI:
2246 case Opcodes::Op_CompareAndSwapL:
2247 case Opcodes::Op_CompareAndSwapP:
2248 case Opcodes::Op_CompareAndSwapN: { // Convert trinary to binary-tree
2249 Node *newval = n->in(MemNode::ValueIn );
2250 Node *oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2251 Node *pair = new BinaryNode( oldval, newval );
2252 n->set_req(MemNode::ValueIn,pair);
2253 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2254 break;
2255 }
2256 case Opcodes::Op_CMoveD: // Convert trinary to binary-tree
2257 case Opcodes::Op_CMoveF:
2258 case Opcodes::Op_CMoveI:
2259 case Opcodes::Op_CMoveL:
2260 case Opcodes::Op_CMoveN:
2261 case Opcodes::Op_CMoveP:
2262 case Opcodes::Op_CMoveVD: {
2263 // Restructure into a binary tree for Matching. It's possible that
2264 // we could move this code up next to the graph reshaping for IfNodes
2265 // or vice-versa, but I do not want to debug this for Ladybird.
2266 // 10/2/2000 CNC.
2267 Node *pair1 = new BinaryNode(n->in(1),n->in(1)->in(1));
2268 n->set_req(1,pair1);
2269 Node *pair2 = new BinaryNode(n->in(2),n->in(3));
2270 n->set_req(2,pair2);
2271 n->del_req(3);
2272 break;
2273 }
2274 case Opcodes::Op_LoopLimit: {
2275 Node *pair1 = new BinaryNode(n->in(1),n->in(2));
2276 n->set_req(1,pair1);
2277 n->set_req(2,n->in(3));
2278 n->del_req(3);
2279 break;
2280 }
2281 case Opcodes::Op_StrEquals:
2282 case Opcodes::Op_StrIndexOfChar: {
2283 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2284 n->set_req(2,pair1);
2285 n->set_req(3,n->in(4));
2286 n->del_req(4);
2287 break;
2288 }
2289 case Opcodes::Op_StrComp:
2290 case Opcodes::Op_StrIndexOf: {
2291 Node *pair1 = new BinaryNode(n->in(2),n->in(3));
2292 n->set_req(2,pair1);
2293 Node *pair2 = new BinaryNode(n->in(4),n->in(5));
2294 n->set_req(3,pair2);
2295 n->del_req(5);
2296 n->del_req(4);
2297 break;
2298 }
2299 case Opcodes::Op_StrCompressedCopy:
2300 case Opcodes::Op_StrInflatedCopy:
2301 case Opcodes::Op_EncodeISOArray: {
2302 // Restructure into a binary tree for Matching.
2303 Node* pair = new BinaryNode(n->in(3), n->in(4));
2304 n->set_req(3, pair);
2305 n->del_req(4);
2306 break;
2307 }
2308 default:
2309 break;
2310 }
2311 }
2312 else {
2313 ShouldNotReachHere();
2314 }
2315 } // end of while (mstack.is_nonempty())
2316 }
2317
2318 #ifdef ASSERT
2319 // machine-independent root to machine-dependent root
2320 void Matcher::dump_old2new_map() {
2321 _old2new_map.dump();
2322 }
2323 #endif
2324
2325 //---------------------------collect_null_checks-------------------------------
2326 // Find null checks in the ideal graph; write a machine-specific node for
2327 // it. Used by later implicit-null-check handling. Actually collects
2328 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2329 // value being tested.
2330 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2331 Node *iff = proj->in(0);
2332 if( iff->Opcode() == Opcodes::Op_If ) {
2333 // During matching If's have Bool & Cmp side-by-side
2334 BoolNode *b = iff->in(1)->as_Bool();
2335 Node *cmp = iff->in(2);
2336 Opcodes opc = cmp->Opcode();
2337 if (opc != Opcodes::Op_CmpP && opc != Opcodes::Op_CmpN) return;
2338
2339 const Type* ct = cmp->in(2)->bottom_type();
2340 if (ct == TypePtr::NULL_PTR ||
2341 (opc == Opcodes::Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2342
2343 bool push_it = false;
2344 if( proj->Opcode() == Opcodes::Op_IfTrue ) {
2345 #ifndef PRODUCT
2346 extern int all_null_checks_found;
2347 all_null_checks_found++;
2348 #endif
2349 if( b->_test._test == BoolTest::ne ) {
2350 push_it = true;
2351 }
2352 } else {
2353 assert( proj->Opcode() == Opcodes::Op_IfFalse, "" );
2354 if( b->_test._test == BoolTest::eq ) {
2355 push_it = true;
2356 }
2357 }
2358 if( push_it ) {
2359 _null_check_tests.push(proj);
2360 Node* val = cmp->in(1);
2361 #ifdef _LP64
2362 if (val->bottom_type()->isa_narrowoop() &&
2363 !Matcher::narrow_oop_use_complex_address()) {
2364 //
2365 // Look for DecodeN node which should be pinned to orig_proj.
2366 // On platforms (Sparc) which can not handle 2 adds
2367 // in addressing mode we have to keep a DecodeN node and
2368 // use it to do implicit NULL check in address.
2369 //
2370 // DecodeN node was pinned to non-null path (orig_proj) during
2371 // CastPP transformation in final_graph_reshaping_impl().
2372 //
2373 uint cnt = orig_proj->outcnt();
2414 // Is a match-tree root, so replace with the matched value
2415 _null_check_tests.map(i+1, new_val);
2416 } else {
2417 // Yank from candidate list
2418 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2419 _null_check_tests.map(i,_null_check_tests[--cnt]);
2420 _null_check_tests.pop();
2421 _null_check_tests.pop();
2422 i-=2;
2423 }
2424 }
2425 }
2426
2427 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2428 // atomic instruction acting as a store_load barrier without any
2429 // intervening volatile load, and thus we don't need a barrier here.
2430 // We retain the Node to act as a compiler ordering barrier.
2431 bool Matcher::post_store_load_barrier(const Node* vmb) {
2432 Compile* C = Compile::current();
2433 assert(vmb->is_MemBar(), "");
2434 assert(vmb->Opcode() != Opcodes::Op_MemBarAcquire && vmb->Opcode() != Opcodes::Op_LoadFence, "");
2435 const MemBarNode* membar = vmb->as_MemBar();
2436
2437 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2438 Node* ctrl = NULL;
2439 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2440 Node* p = membar->fast_out(i);
2441 assert(p->is_Proj(), "only projections here");
2442 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2443 !C->node_arena()->contains(p)) { // Unmatched old-space only
2444 ctrl = p;
2445 break;
2446 }
2447 }
2448 assert((ctrl != NULL), "missing control projection");
2449
2450 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2451 Node *x = ctrl->fast_out(j);
2452 Opcodes xop = x->Opcode();
2453
2454 // We don't need current barrier if we see another or a lock
2455 // before seeing volatile load.
2456 //
2457 // Op_Fastunlock previously appeared in the Op_* list below.
2458 // With the advent of 1-0 lock operations we're no longer guaranteed
2459 // that a monitor exit operation contains a serializing instruction.
2460
2461 if (xop == Opcodes::Op_MemBarVolatile ||
2462 xop == Opcodes::Op_CompareAndExchangeB ||
2463 xop == Opcodes::Op_CompareAndExchangeS ||
2464 xop == Opcodes::Op_CompareAndExchangeI ||
2465 xop == Opcodes::Op_CompareAndExchangeL ||
2466 xop == Opcodes::Op_CompareAndExchangeP ||
2467 xop == Opcodes::Op_CompareAndExchangeN ||
2468 xop == Opcodes::Op_WeakCompareAndSwapB ||
2469 xop == Opcodes::Op_WeakCompareAndSwapS ||
2470 xop == Opcodes::Op_WeakCompareAndSwapL ||
2471 xop == Opcodes::Op_WeakCompareAndSwapP ||
2472 xop == Opcodes::Op_WeakCompareAndSwapN ||
2473 xop == Opcodes::Op_WeakCompareAndSwapI ||
2474 xop == Opcodes::Op_CompareAndSwapB ||
2475 xop == Opcodes::Op_CompareAndSwapS ||
2476 xop == Opcodes::Op_CompareAndSwapL ||
2477 xop == Opcodes::Op_CompareAndSwapP ||
2478 xop == Opcodes::Op_CompareAndSwapN ||
2479 xop == Opcodes::Op_CompareAndSwapI) {
2480 return true;
2481 }
2482
2483 // Op_FastLock previously appeared in the Op_* list above.
2484 // With biased locking we're no longer guaranteed that a monitor
2485 // enter operation contains a serializing instruction.
2486 if ((xop == Opcodes::Op_FastLock) && !UseBiasedLocking) {
2487 return true;
2488 }
2489
2490 if (x->is_MemBar()) {
2491 // We must retain this membar if there is an upcoming volatile
2492 // load, which will be followed by acquire membar.
2493 if (xop == Opcodes::Op_MemBarAcquire || xop == Opcodes::Op_LoadFence) {
2494 return false;
2495 } else {
2496 // For other kinds of barriers, check by pretending we
2497 // are them, and seeing if we can be removed.
2498 return post_store_load_barrier(x->as_MemBar());
2499 }
2500 }
2501
2502 // probably not necessary to check for these
2503 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2504 return false;
2505 }
2506 }
2507 return false;
2508 }
2509
2510 // Check whether node n is a branch to an uncommon trap that we could
2511 // optimize as test with very high branch costs in case of going to
2512 // the uncommon trap. The code must be able to be recompiled to use
2513 // a cheaper test.
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