152 assert(!has_new_node(n), "set only once");
153 _nodes.map(n->_idx, nn);
154 }
155
156 #ifdef ASSERT
157 // Make sure only new nodes are reachable from this node
158 void verify_new_nodes_only(Node* root);
159
160 Node* _mem_node; // Ideal memory node consumed by mach node
161 #endif
162
163 // Mach node for ConP #NULL
164 MachNode* _mach_null;
165
166 void handle_precedence_edges(Node* n, MachNode *mach);
167
168 public:
169 int LabelRootDepth;
170 // Convert ideal machine register to a register mask for spill-loads
171 static const RegMask *idealreg2regmask[];
172 RegMask *idealreg2spillmask [_last_machine_leaf];
173 RegMask *idealreg2debugmask [_last_machine_leaf];
174 RegMask *idealreg2mhdebugmask[_last_machine_leaf];
175 void init_spill_mask( Node *ret );
176 // Convert machine register number to register mask
177 static uint mreg2regmask_max;
178 static RegMask mreg2regmask[];
179 static RegMask STACK_ONLY_mask;
180
181 MachNode* mach_null() const { return _mach_null; }
182
183 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
184 void set_shared( Node *n ) { _shared.set(n->_idx); }
185 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
186 void set_visited( Node *n ) { _visited.set(n->_idx); }
187 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
188 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
189
190 // Mode bit to tell DFA and expand rules whether we are running after
191 // (or during) register selection. Usually, the matcher runs before,
192 // but it will also get called to generate post-allocation spill code.
193 // In this situation, it is a deadly error to attempt to allocate more
194 // temporary registers.
196
197 // Machine register names
198 static const char *regName[];
199 // Machine register encodings
200 static const unsigned char _regEncode[];
201 // Machine Node names
202 const char **_ruleName;
203 // Rules that are cheaper to rematerialize than to spill
204 static const uint _begin_rematerialize;
205 static const uint _end_rematerialize;
206
207 // An array of chars, from 0 to _last_Mach_Reg.
208 // No Save = 'N' (for register windows)
209 // Save on Entry = 'E'
210 // Save on Call = 'C'
211 // Always Save = 'A' (same as SOE + SOC)
212 const char *_register_save_policy;
213 const char *_c_reg_save_policy;
214 // Convert a machine register to a machine register type, so-as to
215 // properly match spill code.
216 const int *_register_save_type;
217 // Maps from machine register to boolean; true if machine register can
218 // be holding a call argument in some signature.
219 static bool can_be_java_arg( int reg );
220 // Maps from machine register to boolean; true if machine register holds
221 // a spillable argument.
222 static bool is_spillable_arg( int reg );
223
224 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
225 // List is valid in the post-matching space.
226 Node_List _null_check_tests;
227 void collect_null_checks( Node *proj, Node *orig_proj );
228 void validate_null_checks( );
229
230 Matcher();
231
232 // Get a projection node at position pos
233 Node* get_projection(uint pos) {
234 return _projection_list[pos];
235 }
236
282
283 // Register number of the stack slot corresponding to the highest incoming
284 // argument on the stack. Per the Big Picture in the AD file, it is:
285 // _old_SP + out_preserve_stack_slots + incoming argument size.
286 OptoReg::Name _in_arg_limit;
287
288 // Register number of the stack slot corresponding to the new SP.
289 // Per the Big Picture in the AD file, it is:
290 // _in_arg_limit + pad0
291 OptoReg::Name _new_SP;
292
293 // Register number of the stack slot corresponding to the highest outgoing
294 // argument on the stack. Per the Big Picture in the AD file, it is:
295 // _new_SP + max outgoing arguments of all calls
296 OptoReg::Name _out_arg_limit;
297
298 OptoRegPair *_parm_regs; // Array of machine registers per argument
299 RegMask *_calling_convention_mask; // Array of RegMasks per argument
300
301 // Does matcher have a match rule for this ideal node?
302 static const bool has_match_rule(int opcode);
303 static const bool _hasMatchRule[_last_opcode];
304
305 // Does matcher have a match rule for this ideal node and is the
306 // predicate (if there is one) true?
307 // NOTE: If this function is used more commonly in the future, ADLC
308 // should generate this one.
309 static const bool match_rule_supported(int opcode);
310
311 // identify extra cases that we might want to provide match rules for
312 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
313 static const bool match_rule_supported_vector(int opcode, int vlen);
314
315 // Some microarchitectures have mask registers used on vectors
316 static const bool has_predicated_vectors(void);
317
318 // Some uarchs have different sized float register resources
319 static const int float_pressure(int default_pressure_threshold);
320
321 // Used to determine if we have fast l2f conversion
322 // USII has it, USIII doesn't
323 static const bool convL2FSupported(void);
324
325 // Vector width in bytes
326 static const int vector_width_in_bytes(BasicType bt);
327
328 // Limits on vector size (number of elements).
329 static const int max_vector_size(const BasicType bt);
330 static const int min_vector_size(const BasicType bt);
331 static const bool vector_size_supported(const BasicType bt, int size) {
332 return (Matcher::max_vector_size(bt) >= size &&
333 Matcher::min_vector_size(bt) <= size);
334 }
335
336 // Vector ideal reg
337 static const int vector_ideal_reg(int len);
338 static const int vector_shift_count_ideal_reg(int len);
339
340 // CPU supports misaligned vectors store/load.
341 static const bool misaligned_vectors_ok();
342
343 // Should original key array reference be passed to AES stubs
344 static const bool pass_original_key_for_aes();
345
346 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
347 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
348 // Depends on the details of 64-bit constant generation on the CPU.
349 static const bool isSimpleConstant64(jlong con);
350
351 // These calls are all generated by the ADLC
352
353 // TRUE - grows up, FALSE - grows down (Intel)
354 virtual bool stack_direction() const;
355
356 // Java-Java calling convention
357 // (what you use when Java calls Java)
358
360 // Sparc probably wants at least double-word (8).
361 static uint stack_alignment_in_bytes();
362 // Alignment of stack, measured in stack slots.
363 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
364 static uint stack_alignment_in_slots() {
365 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
366 }
367
368 // Array mapping arguments to registers. Argument 0 is usually the 'this'
369 // pointer. Registers can include stack-slots and regular registers.
370 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
371
372 // Convert a sig into a calling convention register layout
373 // and find interesting things about it.
374 static OptoReg::Name find_receiver( bool is_outgoing );
375 // Return address register. On Intel it is a stack-slot. On PowerPC
376 // it is the Link register. On Sparc it is r31?
377 virtual OptoReg::Name return_addr() const;
378 RegMask _return_addr_mask;
379 // Return value register. On Intel it is EAX. On Sparc i0/o0.
380 static OptoRegPair return_value(int ideal_reg, bool is_outgoing);
381 static OptoRegPair c_return_value(int ideal_reg, bool is_outgoing);
382 RegMask _return_value_mask;
383 // Inline Cache Register
384 static OptoReg::Name inline_cache_reg();
385 static int inline_cache_reg_encode();
386
387 // Register for DIVI projection of divmodI
388 static RegMask divI_proj_mask();
389 // Register for MODI projection of divmodI
390 static RegMask modI_proj_mask();
391
392 // Register for DIVL projection of divmodL
393 static RegMask divL_proj_mask();
394 // Register for MODL projection of divmodL
395 static RegMask modL_proj_mask();
396
397 // Use hardware DIV instruction when it is faster than
398 // a code which use multiply for division by constant.
399 static bool use_asm_for_ldiv_by_con( jlong divisor );
400
401 static const RegMask method_handle_invoke_SP_save_mask();
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152 assert(!has_new_node(n), "set only once");
153 _nodes.map(n->_idx, nn);
154 }
155
156 #ifdef ASSERT
157 // Make sure only new nodes are reachable from this node
158 void verify_new_nodes_only(Node* root);
159
160 Node* _mem_node; // Ideal memory node consumed by mach node
161 #endif
162
163 // Mach node for ConP #NULL
164 MachNode* _mach_null;
165
166 void handle_precedence_edges(Node* n, MachNode *mach);
167
168 public:
169 int LabelRootDepth;
170 // Convert ideal machine register to a register mask for spill-loads
171 static const RegMask *idealreg2regmask[];
172 RegMask *idealreg2spillmask [static_cast<uint>(Opcodes::_last_machine_leaf)];
173 RegMask *idealreg2debugmask [static_cast<uint>(Opcodes::_last_machine_leaf)];
174 RegMask *idealreg2mhdebugmask[static_cast<uint>(Opcodes::_last_machine_leaf)];
175 void init_spill_mask( Node *ret );
176 // Convert machine register number to register mask
177 static uint mreg2regmask_max;
178 static RegMask mreg2regmask[];
179 static RegMask STACK_ONLY_mask;
180
181 MachNode* mach_null() const { return _mach_null; }
182
183 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
184 void set_shared( Node *n ) { _shared.set(n->_idx); }
185 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
186 void set_visited( Node *n ) { _visited.set(n->_idx); }
187 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
188 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
189
190 // Mode bit to tell DFA and expand rules whether we are running after
191 // (or during) register selection. Usually, the matcher runs before,
192 // but it will also get called to generate post-allocation spill code.
193 // In this situation, it is a deadly error to attempt to allocate more
194 // temporary registers.
196
197 // Machine register names
198 static const char *regName[];
199 // Machine register encodings
200 static const unsigned char _regEncode[];
201 // Machine Node names
202 const char **_ruleName;
203 // Rules that are cheaper to rematerialize than to spill
204 static const uint _begin_rematerialize;
205 static const uint _end_rematerialize;
206
207 // An array of chars, from 0 to _last_Mach_Reg.
208 // No Save = 'N' (for register windows)
209 // Save on Entry = 'E'
210 // Save on Call = 'C'
211 // Always Save = 'A' (same as SOE + SOC)
212 const char *_register_save_policy;
213 const char *_c_reg_save_policy;
214 // Convert a machine register to a machine register type, so-as to
215 // properly match spill code.
216 const Opcodes *_register_save_type;
217 // Maps from machine register to boolean; true if machine register can
218 // be holding a call argument in some signature.
219 static bool can_be_java_arg( int reg );
220 // Maps from machine register to boolean; true if machine register holds
221 // a spillable argument.
222 static bool is_spillable_arg( int reg );
223
224 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
225 // List is valid in the post-matching space.
226 Node_List _null_check_tests;
227 void collect_null_checks( Node *proj, Node *orig_proj );
228 void validate_null_checks( );
229
230 Matcher();
231
232 // Get a projection node at position pos
233 Node* get_projection(uint pos) {
234 return _projection_list[pos];
235 }
236
282
283 // Register number of the stack slot corresponding to the highest incoming
284 // argument on the stack. Per the Big Picture in the AD file, it is:
285 // _old_SP + out_preserve_stack_slots + incoming argument size.
286 OptoReg::Name _in_arg_limit;
287
288 // Register number of the stack slot corresponding to the new SP.
289 // Per the Big Picture in the AD file, it is:
290 // _in_arg_limit + pad0
291 OptoReg::Name _new_SP;
292
293 // Register number of the stack slot corresponding to the highest outgoing
294 // argument on the stack. Per the Big Picture in the AD file, it is:
295 // _new_SP + max outgoing arguments of all calls
296 OptoReg::Name _out_arg_limit;
297
298 OptoRegPair *_parm_regs; // Array of machine registers per argument
299 RegMask *_calling_convention_mask; // Array of RegMasks per argument
300
301 // Does matcher have a match rule for this ideal node?
302 static const bool has_match_rule(Opcodes opcode);
303 static const bool _hasMatchRule[static_cast<uint>(Opcodes::_last_opcode)];
304
305 // Does matcher have a match rule for this ideal node and is the
306 // predicate (if there is one) true?
307 // NOTE: If this function is used more commonly in the future, ADLC
308 // should generate this one.
309 static const bool match_rule_supported(Opcodes opcode);
310
311 // identify extra cases that we might want to provide match rules for
312 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
313 static const bool match_rule_supported_vector(Opcodes opcode, int vlen);
314
315 // Some microarchitectures have mask registers used on vectors
316 static const bool has_predicated_vectors(void);
317
318 // Some uarchs have different sized float register resources
319 static const int float_pressure(int default_pressure_threshold);
320
321 // Used to determine if we have fast l2f conversion
322 // USII has it, USIII doesn't
323 static const bool convL2FSupported(void);
324
325 // Vector width in bytes
326 static const int vector_width_in_bytes(BasicType bt);
327
328 // Limits on vector size (number of elements).
329 static const int max_vector_size(const BasicType bt);
330 static const int min_vector_size(const BasicType bt);
331 static const bool vector_size_supported(const BasicType bt, int size) {
332 return (Matcher::max_vector_size(bt) >= size &&
333 Matcher::min_vector_size(bt) <= size);
334 }
335
336 // Vector ideal reg
337 static const Opcodes vector_ideal_reg(int len);
338 static const Opcodes vector_shift_count_ideal_reg(int len);
339
340 // CPU supports misaligned vectors store/load.
341 static const bool misaligned_vectors_ok();
342
343 // Should original key array reference be passed to AES stubs
344 static const bool pass_original_key_for_aes();
345
346 // Used to determine a "low complexity" 64-bit constant. (Zero is simple.)
347 // The standard of comparison is one (StoreL ConL) vs. two (StoreI ConI).
348 // Depends on the details of 64-bit constant generation on the CPU.
349 static const bool isSimpleConstant64(jlong con);
350
351 // These calls are all generated by the ADLC
352
353 // TRUE - grows up, FALSE - grows down (Intel)
354 virtual bool stack_direction() const;
355
356 // Java-Java calling convention
357 // (what you use when Java calls Java)
358
360 // Sparc probably wants at least double-word (8).
361 static uint stack_alignment_in_bytes();
362 // Alignment of stack, measured in stack slots.
363 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
364 static uint stack_alignment_in_slots() {
365 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
366 }
367
368 // Array mapping arguments to registers. Argument 0 is usually the 'this'
369 // pointer. Registers can include stack-slots and regular registers.
370 static void calling_convention( BasicType *, VMRegPair *, uint len, bool is_outgoing );
371
372 // Convert a sig into a calling convention register layout
373 // and find interesting things about it.
374 static OptoReg::Name find_receiver( bool is_outgoing );
375 // Return address register. On Intel it is a stack-slot. On PowerPC
376 // it is the Link register. On Sparc it is r31?
377 virtual OptoReg::Name return_addr() const;
378 RegMask _return_addr_mask;
379 // Return value register. On Intel it is EAX. On Sparc i0/o0.
380 static OptoRegPair return_value(Opcodes ideal_reg, bool is_outgoing);
381 static OptoRegPair c_return_value(Opcodes ideal_reg, bool is_outgoing);
382 RegMask _return_value_mask;
383 // Inline Cache Register
384 static OptoReg::Name inline_cache_reg();
385 static int inline_cache_reg_encode();
386
387 // Register for DIVI projection of divmodI
388 static RegMask divI_proj_mask();
389 // Register for MODI projection of divmodI
390 static RegMask modI_proj_mask();
391
392 // Register for DIVL projection of divmodL
393 static RegMask divL_proj_mask();
394 // Register for MODL projection of divmodL
395 static RegMask modL_proj_mask();
396
397 // Use hardware DIV instruction when it is faster than
398 // a code which use multiply for division by constant.
399 static bool use_asm_for_ldiv_by_con( jlong divisor );
400
401 static const RegMask method_handle_invoke_SP_save_mask();
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